SAMA5D43_14 Datasheet, PDF (296/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

In order to save power consumption, the division factor can be 1, 2, 4 or 8. The PMC_PCR is a register that
features a command and acts like a mailbox. To write the division factor on a particular peripheral, user needs to
write a WRITE command, the peripheral ID and the chosen division factor. To read the current division factor on a
particular peripheral, user just needs to write the READ command and the peripheral ID.
Code Example to select divider 8 for peripheral 2 and enable its clock:
write_register(PMC_PCR,0x01030102)
Code Example to read the divider of peripheral 4:
write_register(PMC_PCR,0x00000004)
When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically
disabled after a reset.
In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its
last programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the
system.
The bit number within the Peripheral Control registers is the Peripheral Identifier defined at the product level.
Generally, the bit number corresponds to the interrupt source number assigned to the peripheral.
27.12 Programmable Clock Output Controller
The PMC controls two signals to be outputs on external pins PCKx. Each signal can be independently
programmed via the PMC_PCKx registers.
PCKx can be independently selected between the Slow clock (SLCK), the Master Clock (MAINCK), the PLLACK,
the UTMI PLL output and the main clock by writing the CSS field in PMC_PCKx. Each output signal can also be
divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx.
Each output signal can be enabled and disabled by writing a 1 in the corresponding bit, PCKx of PMC_SCER and
PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of
PMC_SCSR.
Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actually what has been
programmed in the Programmable Clock registers.
As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly
recommended to disable the Programmable Clock before any configuration change and to re-enable it after the
change is actually performed.
27.13 Slow Crystal Clock Frequency Monitor
The frequency of the slow clock crystal oscillator can be monitored by means of logic driven by the main RC
oscillator known as a reliable clock source. This function is enabled by configuring the XT32KFME bit of
CKGR_MOR.
An error flag (XT32KERR in PMC_SR) is asserted when the slow clock crystal oscillator frequency is out of the +/-
10% nominal frequency value (i.e., 32768 Hz). The error flag can be cleared only if the slow clock frequency
monitoring is disabled.
The monitored clock frequency is declared invalid if at least four consecutive clock period measurement results are
over the nominal period +/-10%.
Due to the possible frequency variation of the embedded main RC oscillator acting as reference clock for the
monitor logic, any slow clock crystal frequency deviation over +/-10% of the nominal frequency is systematically
reported as an error by means of XT32KERR in PMC_SR. Between -1% and -10% and +1% and +10%, the error
is not systematically reported.
Thus only a crystal running at 32768 Hz frequency ensures that the error flag will not be asserted. The permitted
drift of the crystal is 10000 ppm (1%), which allows any standard crystal to be used.
296
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14