SAMA5D43_14 Datasheet, PDF (489/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

Figure 30-10. Write Cycle
MCK
A[25:2]
NBS0, NBS1,
A0, A1
NWE
NCS
NWE_SETUP
NWE_PULSE
NWE_HOLD
NCS_WR_SETUP
NCS_WR_PULSE
NWE_CYCLE
NCS_WR_HOLD
30.10.3.3 Write Cycle
The write cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on
the address bus to the point where address may change. The total write cycle time is equal to:
NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD,
as well as
NWE_CYCLE = NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD
All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock
cycles. The NWE_CYCLE field is common to both the NWE and NCS signals, thus the timing period is of the same
duration.
NWE_CYCLE, NWE_SETUP, and NWE_PULSE implicitly define the NWE_HOLD value as:
NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE
NWE_CYCLE, NCS_WR_SETUP, and NCS_WR_PULSE implicitly define the NCS_WR_HOLD value as:
NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE
30.10.4 Write Mode
The WRITE_MODE parameter in the HSMC_MODE register of the corresponding chip select indicates which
signal controls the write operation.
30.10.4.1 Write is Controlled by NWE (WRITE_MODE = 1)
Figure 30-11 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is put on the bus
during the pulse and hold steps of the NWE signal. The internal data buffers are switched to output mode after the
NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS.
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14
489