SAMA5D43_14 Datasheet, PDF (291/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

Figure 26-5. UTMI PLL Block Diagram
MAINCK
UPLLEN
UTMI PLL
UPLLCK
SLCK
UPLLCOUNT
UTMI PLL
Counter
LOCKU
Whenever the UTMI PLL is enabled by writing UPLLEN in CKGR_UCKR, the LOCKU bit in PMC_SR is
automatically cleared. The values written in the PLLCOUNT field in CKGR_UCKR are loaded in the UTMI PLL
counter. The UTMI PLL counter then decrements at the speed of the Slow Clock divided by 8 until it reaches 0. At
this time, the LOCKU bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the
number of Slow Clock cycles required to cover the UTMI PLL transient time into the PLLCOUNT field.
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14
291