SAMA5D43_14 Datasheet, PDF (492/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

30.10.7.3 For Read and Write Operations
A null value for pulse parameters is forbidden and may lead to an unpredictable behavior.
In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For
external devices that require setup and hold time between NCS and NRD signals (read), or between NCS and
NWE signals (write), these setup and hold times must be converted into setup and hold times in reference to the
address bus.
30.11 Scrambling/Unscrambling Function
The external data bus D[15:0] can be scrambled in order to prevent intellectual property data located in off-chip
memories from being easily recovered by analyzing data at the package pin level of either the microcontroller or
the memory device.
The scrambling and unscrambling are performed on-the-fly without additional wait states.
The scrambling method depends on two user-configurable key registers, HSMC_KEY1 and HSMC_KEY2. These
key registers are only accessible in write mode.
The key must be securely stored in a reliable non-volatile memory in order to recover data from the off-chip
memory. Any data scrambled with a given key cannot be recovered if the key is lost.
The scrambling/unscrambling function is enabled or disabled by configuring specific bits in the HSMC_OCMS and
the HSMC_TIMINGSx registers. The bit configuration values to enable memory scrambling are summarized in
Table 30-7.
Table 30-7. Scrambling Function Bit Encoding
Memories
Off-chip Memories
NAND Flash with NFC
HSMC_OCMS.SMSE
1
0
Bit Values
HSMC_OCMS.SRSE
0
1
HSMC_TIMINGSx.OCMS
1
0
When the NAND Flash memory content is scrambled, the on-chip NFC SRAM page buffer associated for the
transfer is also scrambled.
30.12 Automatic Wait States
Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention
or operation conflict.
30.12.1 Chip Select Wait States
The SMC always inserts an idle cycle between two transfers on separate chip selects. This idle cycle ensures that
there is no bus contention between the de-activation of one device and the activation of the next one.
During chip select wait state, all control lines are turned inactive: NBS0 to NBS1, NWR0 to NWR1, NCS[0..3], and
NRD lines. They are all set to 1.
Figure 30-13 illustrates a chip select wait state between access on Chip Select 0 and Chip Select 2.
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SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14