SAMA5D43_14 Datasheet, PDF (1184/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

the Status Register (TWI_SR) if the slave does not acknowledge the byte. As with the other status bits, an interrupt
can be generated if enabled in the Interrupt Enable register (TWI_IER). If the slave acknowledges the byte, the
data written in the TWI_THR is then shifted in the internal shifter and transferred. When an acknowledge is
detected, the TXRDY bit is set until a new write in the TWI_THR.
When no more data is written into the TWI_THR, the master generates a STOP condition to end the transfer. A
TXCOMP bit value of one in the TWI_SR indicates that the transfer has completed. See Figure 40-6, Figure 40-7,
and Figure 40-8.
Figure 40-6. Master Write with One Data Byte
TWD S
DADR
W
A
DATA
A
P
TXCOMP
TXRDY
Write THR (DATA)
Figure 40-7. Master Write with Multiple Data Byte
TWD S
DADR
W
A
DATA n
A
TXCOMP
STOP sent automaticaly
(ACK received and TXRDY = 1)
DATA n+5
A
DATA n+x
A
P
TXRDY
Write THR (Data n)
Write THR (Data n+1)
Write THR (Data n+x)
Last data sent
STOP sent automaticaly
(ACK received and TXRDY = 1)
Figure 40-8. Master Write with One Byte Internal Address and Multiple Data Bytes
TWD S
DADR
W A IADR(7:0) A
DATA n
A
DATA n+5 A DATA n+x A P
TXCOMP
TXRDY
Write THR (Data n)
Write THR (Data n+1) Write THR (Data n+x) STOP sent automaticaly
Last data sent (ACK received and TXRDY = 1)
40.7.3.5 Master Receiver Mode
The read sequence begins by setting the START bit. After the START condition has been sent, the master sends
a 7-bit slave address to notify the slave device. The bit following the slave address indicates the transfer
direction—1 in this case (MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master
1184
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14