EF4442 Datasheet, PDF (9/21 Pages) ATMEL Corporation – ARINC 429 Multi-channel Buffer Receiver (RTA) (N Channel, Silicon Gate)

EF4442
Figure 3. Bit Correspondence
Acquisition or transmission flow
Acquisition register 31
Buffer register
7 RT3
0 ₇ RT2
0 ₇ RT1
07
LABEL
0
Bus D (0:7)
Control C (0:7)
Status S (0:7)
Transmit shift
Register
Enable and synchro register
Divider by n
7
0
7
0
7
4
0
RT3
RT2
RT1
LABEL
V6
0
7
1
Programming in B Mode
(MODE = 1)
When in B mode, programming is done by hardware. The number of high speed chan-
nels is programmed on IRQ/V pin (see Table 4).
The synchro register is set to 5 for high speed channels and to 32 for low speed chan-
nels. This corresponds to a nominal Ø clock frequency of 2 MHz and transmission
frequencies of 12 to 14.5 kHz for low speed and of 99 to 101 kHz for high speed.
Table 4. Programming of the IRQ/Vpin
IRQ/V
0: Low impedance
0: High impedance
1: Low impedance
1: High impedance
High Speed Channel Numbers
-
0
0, 1
0, 1, 2
Parity Check
Initialization
If the MODE pin senses a high impedance (typ. > 10 kW) the circuit checks the parity of
the messages for each receive channel. If the number of received 1’s in a message is
even, the transfer is not done and the message is discarded (odd parity).
When transmitting, the parity bit value is computed and loaded by the microprocessor or
is the value of the received test message.
If the MODE pin is directly strapped to V_CC or V_SS, parity check is not done.
On power-on or when the RESET pin is set to 0, the following registers are reset to 0:
• control register
• status register
• the 4 label registers of the receive channels
• the 4 synchro registers.
The first gap after initialization is also ignored for each channel because acquired data
could not be error-free.
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2112A–HIREL–11/02