EF4442 Datasheet, PDF (8/21 Pages) ATMEL Corporation – ARINC 429 Multi-channel Buffer Receiver (RTA) (N Channel, Silicon Gate)

Table 2. Addressing with CS = 0
RW/INH
Read
1
Write
0
A1 A0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Direct Addressing
—
—
—
Status
—
Control
Not used
—
Channel Addressing With
the Control Register
RT1
RT2
RT3
—
Synchro and divider by n
—
—
Label
Table 3. Channel Addressing by the Control Register
C0
C1
C2
C3
1
x
x
x
0
1
x
x
0
0
1
x
0
0
0
1
Channel Number
channel 0
channel 1
channel 2
channel 3
The gap detection counters are incremented on each Ø divided by 8 clock period, if n is
the synchro register value, the minimum detected gap length is (8n - 4) ± 4 Ø clock
periods.
C4 to C7 bits are independently interpreted.
C4: Pile loading if A0 - A1 = 11 and divider by n if A0 - A1 = 00.
The loading of the 4 bytes to be transmitted should be done immediately after position-
ing C4 to 1, this operation resetting the pile index at the level of the label byte.
C5:Transmission start
C6: Test mode
C7: Transmit channel interrupt mask
8 EF4442
2112A–HIREL–11/02