EF4442 Datasheet, PDF (7/21 Pages) ATMEL Corporation – ARINC 429 Multi-channel Buffer Receiver (RTA) (N Channel, Silicon Gate)

EF4442
Operation of the
Transmit Channel
(only in A mode)
The transmit channel is composed of a 32-bit shift register and a programmable divider.
The operation of this channel is controlled by the control register (C0 - C7).
C4 selects the program of the transmit channel (see “Programming In A Mode (MODE =
0)” on page 7). The 4 bytes of the shift register are loaded (including the microprocessor
computed parity bit). So is the divider by n register byte.
The latter generates a divided by n frequency square wave, n being the programmed
value (the least significant bit being always set to 0).
Transmission starts when C5 is set to 1. The data of the shift register is then available
on the 0 and 1 lines of the channel and is clocked out at the chosen frequency.
The shift register is also feed forwarded so that data should not be lost. After the trans-
mission of the 32nd bit, C5 is reset. The S4 bit is set to 1. It will be reset when C4 will be
positioned to 1.
The S7 bit of the status register is set to 1 during the transmission time.
If C5 is set to 1 after transmission of the 32nd bit, the message is retransmitted after 4
transmit clock periods. The S4 status bit will also be reset when control bit C4 is set to 1.
C6 is used for starting the receive channel testing. This test cannot be done during the
reception of a message. If C6 = 1 the transmission channel signals are switched to the
inputs of the control register selected receive channel. C6 is reset by any access to the
control register.
C7 is a mask bit of the S4 bit of the status register. If C7 = 0 and S4 = 1, the IRQ line will
be activated. If C7 = 1, the IRQ line will not be activated by S4.
Note: C5 and C6 should be programmed at the same time in order to avoid transmission or test
errors.
Programming In A Mode
(MODE = 0)
When seen from the microprocessor, the circuit looks like 4 addresses (“read” or
“write”).
Addressing any register of a channel is done in two steps:
• channel addressing by the control register
• byte of the selected channel addressing
Thus, programming of the synchro registers or the labels and reading of the 24-bit buff-
ers or the status register are possible.
Loading of the transmit channel shift register is done through successive writing of the 4
bytes, the first being the label then RT₁, RT₂, RT₃. The addresses of the 4 bytes are
generated by an internal modulo-4 counter which is reset by any addressing of the con-
trol register (see Table 2 - Addressing with CS = 0 and Table 3 - Addressing of the
channels by the control register).
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