EF4442 Datasheet, PDF(3/21 Page) ATMEL Corporation – ARINC 429 Multi-channel Buffer Receiver (RTA) (N Channel, Silicon Gate)

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EF4442 Datasheet, PDF (3/21 Pages) ATMEL Corporation – ARINC 429 Multi-channel Buffer Receiver (RTA) (N Channel, Silicon Gate)

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EF4442

Table 1. Pin Description (Continued)

Name

Number Description

This input receives the clock signal from the circuit which corresponds to the phase Ã2 of the microprocessor clock.

This tristate input/output is connected to the eighth line of the data bus.

This tristate input/output is connected to the seventh line of the data bus.

This tristate input/output is connected to the sixth line of the data bus.

This tristate input/output is connected to the fifth line of the data bus.

VCC

This pin is connected to the positive side of the power supply (+5V).

This tristate input/output is connected to the fourth line of the data bus.

This tristate input/output is connected to the third line of the data bus.

This tristate input/output is connected to the second line of the data bus.

This tristate input/output is connected to the first line of the data bus.

This input receives the logic â0â clock from the signal shaping/separation subsystem of the first ARINC channel.

This input receives the logic â1â clock from the signal shaping/separation subsystem of the first ARINC channel.

This input receives the logic â0â clock from the signal shaping/separation subsystem of the second ARINC channel.

This input receives the logic â1â clock from the signal shaping/separation subsystem of the second ARINC channel.

This input receives the logic â0â clock from the signal shaping/separation subsystem of the third ARINC channel.

This input receives the logic â1â clock from the signal shaping/separation subsystem of the third ARINC channel.

This input receives the logic â0â clock from the signal shaping/separation subsystem of the fourth ARINC channel.

This input receives the logic â1â clock from the signal shaping/separation subsystem of the fourth ARINC channel.

IRQ/V

In A mode, this pin (active when low) constitutes an open drain output delivering the signal for interrupting the

microprocessor.

In B mode, this pin is an input used to program the number of high speed channels.

Mode This input is used to program the operating mode (A or B) of the circuit and also to enable or disable this parity check.

Description of

Registers

General Registers

Status Register

The EF4442 circuit features three types of internal register:

â¢ Registers concerned with general circuit operation,

â¢ Registers specific to the transmit channel,

â¢ Registers specific to each receive channel.

This register is used only when the circuit is programmed in A mode. Its contents inform

the microprocessor about the status of the circuit functions. Bits S0 and S4 activate out-

put IRQ when at 1 (except S4 which is maskable - cf. description of control register).

Bits S0 and S3 at 1 indicate that the channel with the address which corresponds to the

rank of the bit has received a correct message (label recognized and correct parity in the

case of a circuit programmed to check the parity of messages).

Each bit is reset to 0 on reading the registers of the corresponding channel.

In transmit mode, bit S4 of the status register is set to 1 when transmission of the mes-

sage is terminated.

2112AâHIRELâ11/02

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