EF4442 Datasheet, PDF (6/21 Pages) ATMEL Corporation – ARINC 429 Multi-channel Buffer Receiver (RTA) (N Channel, Silicon Gate)

Then:
• When in A Mode
The first 8 bits (M0-M7) that are received, are bits compared to a programmed word
(label), this for each channel. If identical, the 24 other bits of the shift register are trans-
ferred in a 24-bit buffer register. The corresponding status bit is switched to 1 and the
IRQ line is activated (IRQ = 0).
If the channel enable bit is in the low state, transfer is not executed and the IRQ line is
not activated.
• When in B Mode
All the shift register bits are transferred in the label and the 24-bit buffer register.
Transfers are inhibited if the message parity is wrong in either mode (even number of
bits in the high state) and if the circuit is programmed for parity check (Mode pin).
This last one generates a Ø + n frequency square wave, n being the programmed value
(the least significant bit being always set to 0).
Then successively addresses the 8-bit bytes of the 24-bit buffer which are then available
on the bus (D0-D7).
Reading the last byte resets the corresponding status byte to the low state.
The transfer from the receive register to the buffer register is inhibited from the “read”
addressing of the channel (first or second byte) to the end of the last byte reading.
• When in B Mode
A divide by 4 counter is incremented on each Ø clock period and successively
addresses the 4 channels. When the circuit is selected (CS = 0) and when A0 - A1 = 11,
the label of the addressed channel is available on the bus (D0 - D7), as well as the
channel number on the N0-N1 outputs.
Counting is inhibited when RW/INH is in the high state. If the circuit is selected, the three
bytes of the buffer register are then available on the bus when addressed through A0 -
A1 in the same way as A mode.
The transfer from the receive register to the buffer register is done in the same way as
A mode.
In order to read the message corresponding to label received, CS has to stay activated
to 0 during the reading of label and message RT₁ - RT₃ (minimum CS = 0 during the
reading of the label and RT₁).
However CS has to stay activated to 0 during less than 30 clock periods of PHI (Ø).
6 EF4442
2112A–HIREL–11/02