EF4442 Datasheet, PDF (5/21 Pages) ATMEL Corporation – ARINC 429 Multi-channel Buffer Receiver (RTA) (N Channel, Silicon Gate)

EF4442
Input Register
Label Register
Buffer Register
This 32-bit shift register receives the data corresponding to the messages. The mes-
sage received is transferred into the registers on its output side if:
• a gap detection signal has previously occurred,
• the registers which will receive the transferred data are not being read,
• the parity of the received message is correct if the circuit is programmed with the
parity check enabled,
• the enable bit of the synchronization/enable register is set to 1 (A mode only),
• in A mode, the first eight bits received correspond to the programmed label (cf.
description of label register).
In A mode, this eight-bit register is programmed by the microprocessor. It contains the
label to be recognized.
In B mode, this register receives the first eight bits of the received message transferred
from the input register.
In this case, this register may be read by the external automatic scanning device.
This 24-bit register receives data transferred from the input register.
It may be read by the microprocessor in A mode or by the external automatic scanning
device in B mode.
Circuit Operation
Logic Convention
Operation of a Receive
Channel
Data Acquisition
“1” (high state) = most positive level
“0” (low state) = most negative level
Serial data is received on the “low” and the “high” lines (Hi and Li inputs). The Clock is
reconstructed by OR-ing these inputs. Data is then directed towards a 32-bit shift regis-
ter. Parity is computed. The reconstructed clock fall edge resets the message
synchronization counter. This counter is incremented on each Ø: 8 clock period and
delivers a word synchronization signal (gap) as described below (Figure 2) when read-
ing a programmed value.
Figure 2. Gap Detection
Clock
max
gap
Counter
0
Synchro
Predetermined value
The predetermined value together with an enable bit is loaded in the internal syn-
chro/validation register when in A mode; it is chosen between two hardware
programmed values when in B mode, according to the IRQ/V pin.
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