EF4442 Datasheet, PDF (4/21 Pages) ATMEL Corporation – ARINC 429 Multi-channel Buffer Receiver (RTA) (N Channel, Silicon Gate)

Bit S4 is reset to 0 when control bit C4 (see below) is a 1.
Bits S5 and S6 are not used.
Bit S7 is at 1 throughout transmission.
Control Register
This eight-bit register (C0-C7) monitors operation of the circuit in A mode.
In receive mode, bits C0-C3 select the corresponding channels for writing or reading
when set to 1 by the microprocessor.
Bit C4 at 1 enables programming of the transmit channel (data to send and transmission
speed). The setting of bit C4 to 1 resets to 0 the index of the four-byte stack constituting
the message to send.
Bit C5 at 1 is used to initiate transmission of the message. It is set to 0 when transmis-
sion is terminated.
Bit C6 at 1 simultaneously with bit C5 at 1 loops back the transmitted data to the input of
the receive channel selected by bits C0-C3, for test purposes. It is set to 0 by any control
register access.
Bit C7 at 1 masks status bit S4 and thus prevents activation of output IRQ.
Transmit Channel
Registers (A mode only)
Programmable Divider
Register
This eight-bit register is programmed by the microprocessor and contains the value n of
the division ratio (the least significant bit is always considered to be at 0).
The programmable divider generates a clock signal at a frequency equal to clock Ø
divided by n.
Transmit Register
This 32-bit shift register may be programmed in four phases by the microprocessor. This
writing must be effected immediately after the setting to 1 of control bit C4 (cf. descrip-
tion of control register). This resets to zero the index of the 4-byte stack.
The transmit register shifts the data present in it to the outputs in accordance with the
states of the bits in the control register.
Receive Channel
Registers
Each receive channel comprises the following registers:
Synchronization/Enable
Register
This eight-bit register is programmable by the microprocessor.
The most significant bit (bit 7) is used, in A mode only, to disable the transfer of data at
the input into the buffer register (cf. description of these two registers). The channel
affected is then seen as being out of service.
The other seven bits (bits 0 - 6) select the value of the time-delay used to detect the
presence of a “gap”. This is the space between two consecutive messages, the mini-
mum duration of which is four periods of the transmit clock. This value is loaded into the
register by the microprocessor, in A mode, at the same time as the enable bit.
In B mode, this value is selected from two hardwired values, according to the state on
pin IRQ/V.
If n is the programmed value, the gap detection time-delay will be (8n - 4) ± 4 period of
clock Ø.
4 EF4442
2112A–HIREL–11/02