SAM4C_14 Datasheet, PDF (699/1303 Pages) ATMEL Corporation – Atmel | SMART ARM-based Flash MCU

 Delay between consecutive transfers—independently programmable for each chip select by writing the
DLYBCT field. The time required by the SPI slave device to process received data is managed through
DLYBCT. This time depends on the SPI slave system activity.
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time.
Figure 33-9. Programmable Delays
Chip Select 1
Chip Select 2
SPCK
DLYBCS DLYBS
DLYBCT
DLYBCT
33.7.3.5 Peripheral Selection
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all NPCS
signals are high before and after each transfer.
 Fixed Peripheral Select Mode: SPI exchanges data with only one peripheral.
Fixed peripheral select mode is enabled by writing the PS bit to zero in the SPI_MR. In this case, the current
peripheral is defined by the PCS field in the SPI_MR and the PCS field in the SPI_TDR has no effect.
 Variable Peripheral Select Mode: Data can be exchanged with more than one peripheral without having to
reprogram the NPCS field in the SPI_MR.
Variable peripheral select mode is enabled by setting the PS bit to 1 in the SPI_MR. The PCS field in the
SPI_TDR is used to select the current peripheral. This means that the peripheral selection can be defined for
each new data. The value to write in the SPI_TDR has the following format:
[xxxxxxx(7-bit) + LASTXFER(1-bit)⁽¹⁾+ xxxx(4-bit) + PCS (4-bit) + DATA (8 to 16-bit)] with PCS equals the
chip select to assert, as defined in Section 33.8.4 “SPI Transmit Data Register” and LASTXFER bit at 0 or 1
depending on the CSAAT bit.
Note: 1. Optional
CSAAT, LASTXFER and CSNAAT bits are discussed in Section 33.7.3.9 “Peripheral Deselection with PDC”.
If LASTXFER is used, the command must be issued before writing the last character. Instead of LASTXFER,
the user can use the SPIDIS command. After the end of the PDC transfer, it is necessary to wait for the
TXEMPTY flag and then write SPIDIS into the SPI Control Register (SPI_CR). This does not change the
configuration register values). The NPCS is disabled after the last character transfer. Then, another PDC
transfer can be started if the SPIEN has previously been written in the SPI_CR.
33.7.3.6 SPI Peripheral DMA Controller (PDC)
In both Fixed and Variable peripheral select modes, the Peripheral DMA Controller (PDC) can be used to reduce
processor overhead.
The fixed peripheral selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means,
as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, if the
peripheral selection is modified, the SPI_MR must be reprogrammed.
SAM4C Series [DATASHEET]
Atmel-11102E-ATARM-SAM4C32-SAM4C16-SAM4C8-Datasheet_06-Oct-14
699