SAM4C_14 Datasheet, PDF (100/1303 Pages) ATMEL Corporation – Atmel | SMART ARM-based Flash MCU

12.6.3 Instruction Descriptions
12.6.3.1 Operands
An instruction operand can be an ARM register, a constant, or another instruction-specific parameter. Instructions
act on the operands and often store the result in a destination register. When there is a destination register in the
instruction, it is usually specified before the operands.
Operands in some instructions are flexible, can either be a register or a constant. See “Flexible Second Operand” .
12.6.3.2 Restrictions when Using PC or SP
Many instructions have restrictions on whether the Program Counter (PC) or Stack Pointer (SP) for the operands
or destination register can be used. See instruction descriptions for more information.
Note: Bit[0] of any address written to the PC with a BX, BLX, LDM, LDR, or POP instruction must be 1 for correct execution,
because this bit indicates the required instruction set, and the Cortex-M4 processor only supports Thumb instructions.
12.6.3.3 Flexible Second Operand
Many general data processing instructions have a flexible second operand. This is shown as Operand2 in the
descriptions of the syntax of each instruction.
Operand2 can be a:
 “Constant”
 “Register with Optional Shift”
Constant
Specify an Operand2 constant in the form:
#constant
where constant can be:
 Any constant that can be produced by shifting an 8-bit value left by any number of bits within a 32-bit word
 Any constant of the form 0x00XY00XY
 Any constant of the form 0xXY00XY00
 Any constant of the form 0xXYXYXYXY.
Note: In the constants shown above, X and Y are hexadecimal digits.
In addition, in a small number of instructions, constant can take a wider range of values. These are described in
the individual instruction descriptions.
When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS,
TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be
produced by shifting an 8-bit value. These instructions do not affect the carry flag if Operand2 is any other
constant.
Instruction Substitution
The assembler might be able to produce an equivalent instruction in cases where the user specifies a constant
that is not permitted. For example, an assembler might assemble the instruction CMP Rd, #0xFFFFFFFE as the
equivalent instruction CMN Rd, #0x2.
Register with Optional Shift
Specify an Operand2 register in the form:
Rm {, shift}
where:
Rm
is the register holding the data for the second operand.
shift
is an optional shift to be applied to Rm. It can be one of:
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SAM4C Series [DATASHEET]
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