SAM4C_14 Datasheet, PDF (397/1303 Pages) ATMEL Corporation – Atmel | SMART ARM-based Flash MCU

20.4 Supply Controller Functional Description
20.4.1 Supply Controller Overview
The device can be divided into two power supply areas:
 The backup VDDBU_SW power supply that includes the Supply Controller, a part of the Reset Controller,
the slow clock switch, the general-purpose backup registers, the supply monitor and the clock which
includes the Real-time Timer and the Real-time Clock.
 The core power supply that includes the other part of the Reset Controller, the Brownout Detector, the
processor, the SRAM memory, the Flash memory and the peripherals.
The SUPC controls the core power supply and intervenes when the VDDBU_SW power supply rises (when the
system is starting) or when the backup Low-power mode is entered.
The SUPC also integrates the slow clock generator which is based on a 32 kHz crystal oscillator and an embedded
32 kHz RC oscillator. The slow clock defaults to the RC oscillator, but the software can enable the crystal oscillator
and select it as the slow clock source.
The SUPC and the VDDBU_SW power supply have a reset circuitry based on a zero-power power-on reset cell.
The zero-power power-on reset allows the SUPC to start properly as soon as the VDDBU_SW voltage becomes
valid.
At start-up of the system, once the backup voltage VDDBU_SW is valid and the embedded 32 kHz RC oscillator is
stabilized, the SUPC starts up the core voltage regulator and ties the SHDN pin to VDDBU. Once the VDDCORE
voltage is valid, it releases the system reset signal (vddcore_nreset) to the RSTC. The RSTC module then
releases the sub-system 0 reset signals (proc_nreset and periph_nreset). Note that the sub-sytem 1 remains in
reset after power-up.
Once the system has started, the user can program a supply monitor and/or a brownout detector. If a powerfail
condition occurs on either VDDIO or on VDDCORE power supplies, the SUPC asserts the system reset signal
(vddcore_nreset). This signal is released when the powerfail condition is cleared.
When the backup Low-power mode is entered, the SUPC sequentially asserts the system reset signal and
disables the voltage regulator, in order to maintain only the VDDBU_SW power supply. Current consumption is
reduced to less than one microamp for the backup part retention. Exit from this mode is possible on multiple wake-
up sources including an event on the FWUP pin or WKUPx pins, or a clock alarm. To exit this mode, the SUPC
operates in the same way as system start-up by enabling the core voltage regulator and the SHDN pin.
SAM4C Series [DATASHEET]
Atmel-11102E-ATARM-SAM4C32-SAM4C16-SAM4C8-Datasheet_06-Oct-14
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