SAM4C_14 Datasheet, PDF (332/1303 Pages) ATMEL Corporation – Atmel | SMART ARM-based Flash MCU

Except for debug purposes, PERRST must always be used in conjunction with PROCRST (PERRST and
PROCRST set both at 1 simultaneously).
 RSTC_CPMR.CPROCEN: Writing a 0 to CPROCEN resets the coprocessor only.
 RSTC_CPMR.CPEREN: Writing a 0 to CPEREN resets all the embedded peripherals associated to
coprocessor whereas the processor peripherals are not reset.
 RSTC_CR.EXTRST: Writing a 1 to EXTRST asserts low the NRST pin during a time defined by the field
RSTC_MR.ERSTL.
The software reset is entered if at least one of these bits is set by the software. All these commands can be
performed independently or simultaneously. The software reset lasts three slow clock cycles.
The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master
Clock (MCK). They are released when the software reset has ended, i.e., synchronously to SLCK.
If EXTRST is set, the nrst_out signal is asserted depending on the configuration of field RSTC_MR.ERSTL.
However, the resulting falling edge on NRST does not lead to a user reset.
If and only if the PROCRST bit is set, the Reset Controller reports the software status in field RSTC_SR.RSTTYP.
Other software resets are not reported in RSTTYP.
As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the
RSTC_SR. SRCMP is cleared at the end of the software reset. No other software reset can be performed while the
SRCMP bit is set, and writing any value in the RSTC_CR has no effect.
Figure 15-5. Software Reset
SLCK
MCK
Write RSTC_CR
proc_nreset
if PROCRST=1
RSTTYP
periph_nreset
if PERRST=1
NRST
(nrst_out)
if EXTRST=1
SRCMP in RSTC_SR
Any
Freq.
Resynch. Processor Startup
1 cycle
= 2 cycles
Any
XXX
0x3 = Software Reset
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
15.4.3.5 User Reset
The user reset is entered when a low level is detected on the NRST pin and bit URSTEN in the RSTC_MR is at 1.
The NRST input signal is resynchronized with SLCK to insure proper behavior of the system.
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SAM4C Series [DATASHEET]
Atmel-11102E-ATARM-SAM4C32-SAM4C16-SAM4C8-Datasheet_06-Oct-14