SAM4C_14 Datasheet, PDF (692/1303 Pages) ATMEL Corporation – Atmel | SMART ARM-based Flash MCU

33.6.3 Interrupt
The SPI interface has an interrupt line connected to the interrupt controller. Handling the SPI interrupt requires
programming the interrupt controller before configuring the SPI.
Table 33-3. Peripheral IDs
Instance
ID
SPI0
21
SPI1
40
33.6.4 Peripheral DMA Controller (PDC)
The SPI interface can be used in conjunction with the PDC in order to reduce processor overhead. For a full
description of the PDC, refer to the corresponding section in the full datasheet.
33.7 Functional Description
33.7.1 Modes of Operation
The SPI operates in Master mode or in Slave mode.
 The SPI operates in Master mode by writing a 1 to the MSTR bit in the SPI Mode Register (SPI_MR):
̶ Pins NPCS0 to NPCS3 are all configured as outputs
̶ The SPCK pin is driven
̶ The MISO line is wired on the receiver input
̶ The MOSI line is driven as an output by the transmitter.
 The SPI operates in Slave mode if the MSTR bit in the SPI_MR is written to 0:
̶ The MISO line is driven by the transmitter output
̶ The MOSI line is wired on the receiver input
̶ The SPCK pin is driven by the transmitter to synchronize the receiver.
̶ The NPCS0 pin becomes an input, and is used as a slave select signal (NSS)
̶ NPCS1 to NPCS3 are not driven and can be used for other purposes.
The data transfers are identically programmable for both modes of operations. The baud rate generator is
activated only in Master mode.
33.7.2 Data Transfer
Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the
CPOL bit in the SPI Chip Select register (SPI_CSR). The clock phase is programmed with the NCPHA bit. These
two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two
parameters has two possible states, resulting in four possible combinations that are incompatible with one another.
Consequently, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves
are connected and require different configurations, the master must reconfigure itself each time it needs to
communicate with a different slave.
Table 33-4 shows the four modes and corresponding parameter settings.
692
SAM4C Series [DATASHEET]
Atmel-11102E-ATARM-SAM4C32-SAM4C16-SAM4C8-Datasheet_06-Oct-14