SAM4C_14 Datasheet, PDF (1052/1303 Pages) ATMEL Corporation – Atmel | SMART ARM-based Flash MCU

Figure 42-4. Region Descriptor
Main List
ICMDSCR
Region 3 Descriptor
Region 2 Descriptor
Region 1 Descriptor
Region 0 Descriptor
Optional Region 0 Secondary List
End of Region 0
0x00C Region NEXT
0x008 Region CTRL
0x004 Region CFG
0x000 Region ADDR
0x00C Region NEXT
0x008 Region CTRL
0x004 Unused
0x000 Region ADDR
The ICM integrates a Secure Hash Algorithm Engine (SHA). This module requires a message padded according to
FIPS180-2 specification. The SHA module produces an N-bit message digest each time a block is read and a
processing period ends. N is 160 for SHA1, 224 for SHA224, 256 for SHA256.
42.5.1 ICM Region Descriptor Structure
The ICM Region Descriptor Area is a contiguous area of system memory that the controller and the processor can
access. When the ICM controller is activated, the controller performs a descriptor fetch operation at *(ICM_DSCR)
address. If the Main List contains more than one descriptor (i.e., more than one region is to be monitored), the
fetch address is *(ICM_DSCR) + (RID<<4) where RID is the region identifier.
Table 42-2. Region Descriptor Structure (Main List)
Offset
Structure Member
ICM_DSCR+0x000+RID*(0x10)
ICM Region Start Address
ICM_DSCR+0x004+RID*(0x10)
ICM Region Configuration
ICM_DSCR+0x008+RID*(0x10)
ICM Region Control
ICM_DSCR+0x00C+RID*(0x10) ICM Region Next Address
Name
ICM_RADDR
ICM_RCFG
ICM_RCTRL
ICM_RNEXT
1052
SAM4C Series [DATASHEET]
Atmel-11102E-ATARM-SAM4C32-SAM4C16-SAM4C8-Datasheet_06-Oct-14