SAM4C_14 Datasheet, PDF (1146/1303 Pages) ATMEL Corporation – Atmel | SMART ARM-based Flash MCU

1: Set when USBFS_DEVEPTIERx.NAKINES = 1. This enables the NAKed IN interrupt (USBFS_DEVEPTISRx.NAKINI).
• OVERFE: Overflow Interrupt
0: Cleared when USBFS_DEVEPTIDRx.OVERFEC = 1. This disables the Overflow interrupt
(USBFS_DEVEPTISRx.OVERFI).
1: Set when USBFS_DEVEPTIERx.OVERFES = 1. This enables the Overflow interrupt (USBFS_DEVEPTISRx.OVERFI).
• STALLEDE: STALLed Interrupt
0: Cleared when USBFS_DEVEPTIDRx.STALLEDEC = 1. This disables the STALLed interrupt
(USBFS_DEVEPTISRx.STALLEDI).
1: Set when USBFS_DEVEPTIERx.STALLEDES = 1. This enables the STALLed interrupt
(USBFS_DEVEPTISRx.STALLEDI).
• SHORTPACKETE: Short Packet Interrupt
0: Cleared when USBFS_DEVEPTIDRx.SHORTPACKETEC = 1. This disables the Short Packet interrupt
(USBFS_DEVEPTISRx.SHORTPACKET).
1: Set when USBFS_DEVEPTIERx.SHORTPACKETES = 1. This enables the Short Packet interrupt
(USBFS_DEVEPTISRx.SHORTPACKET).
If this bit is set for non-control IN endpoints, a short packet transmission is guaranteed upon ending a DMA transfer, thus
signaling an end of isochronous frame or a bulk or interrupt end of transfer, provided that the End of DMA Buffer Output
Enable (END_B_EN) bit and the Automatic Switch (AUTOSW) bit = 1.
• NBUSYBKE: Number of Busy Banks Interrupt
0: Cleared when USBFS_DEVEPTIDRx.NBUSYBKEC = 0. This disables the Number of Busy Banks interrupt
(USBFS_DEVEPTISRx.NBUSYBK).
1: Set when USBFS_DEVEPTIERx.NBUSYBKES = 1. This enables the Number of Busy Banks interrupt
(USBFS_DEVEPTISRx.NBUSYBK).
• KILLBK: Kill IN Bank
This bit is set when USBFS_DEVEPTIERx.KILLBKS = 1. This kills the last written bank.
This bit is cleared when the bank is killed.
Caution: The bank is really cleared when the “kill packet” procedure is accepted by the USBFS core. This bit is automati-
cally cleared after the end of the procedure:
The bank is really killed: USBFS_DEVEPTISRx.NBUSYBK is decremented.
The bank is not cleared but sent (IN transfer): USBFS_DEVEPTISRx.NBUSYBK is decremented.
The bank is not cleared because it was empty.
The user should wait for this bit to be cleared before trying to kill another packet.
This kill request is refused if at the same time an IN token is coming and the last bank is the current one being sent on the
USB line. If at least two banks are ready to be sent, there is no problem to kill a packet even if an IN token is coming.
Indeed, in this case, the current bank is sent (IN transfer) while the last bank is killed.
• FIFOCON: FIFO Control
For control endpoints:
The FIFOCON and RWALL bits are irrelevant. Therefore, the software never uses them on these endpoints. When read,
their value is always 0.
For IN endpoints:
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SAM4C Series [DATASHEET]
Atmel-11102E-ATARM-SAM4C32-SAM4C16-SAM4C8-Datasheet_06-Oct-14