SAM4C_14 Datasheet, PDF (398/1303 Pages) ATMEL Corporation – Atmel | SMART ARM-based Flash MCU

20.4.2 Slow Clock Generator
The SUPC embeds a slow clock generator that is supplied with the VDDBU_SW power supply. As soon as
VDDBU_SW is supplied, both the crystal oscillator and the embedded RC oscillator are powered up, but only the
embedded RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100 µs).
The user can select the crystal oscillator to be the source of the slow clock, as it provides a more accurate
frequency. The command is executed by writing the Supply Controller Control register (SUPC_CR) with the
XTALSEL bit at 1, resulting in the following sequence:
1. The crystal oscillator is enabled.
2. A number of slow RC oscillator clock periods is counted to cover the start-up time of the crystal oscillator
(refer to the electrical characteristics for information on 32 kHz crystal oscillator start-up time).
3. The slow clock is switched to the output of the crystal oscillator.
4. The RC oscillator is disabled to save power.
The switching time may vary depending on the slow RC oscillator clock frequency range. The switch of the slow
clock source is glitch-free. The OSCSEL bit of the Supply Controller Status register (SUPC_SR) indicates that the
switchover has completed.
Reverting to the RC oscillator is only possible by shutting down the VDDBU_SW power supply.
If the crystal oscillator is not needed, the XIN32 and XOUT32 pins should be left unconnected.
The user can also put the crystal oscillator in Bypass mode instead of connecting a crystal. In this case, the user
has to provide the external clock signal on XIN32. For details of input characteristics of the XIN32 pin, see the
section “Electrical Characteristics”. To enter Bypass mode, the OSCBYPASS bit of the Supply Controller Mode
register (SUPC_MR) must be set to 1 before writing a 1 to the bit XTALSEL.
20.4.3 Core Voltage Regulator Control/Low-Power Backup Mode
The SUPC can be used to control the embedded voltage regulator.
The voltage regulator automatically adapts its quiescent current depending on the required load current. For
details, see the section “Electrical Characteristics”.
The voltage regulator can be switched off and the device put in Backup mode by setting the bit VROFF in
SUPC_CR.
This asserts the system reset signal after the write resynchronization time, which lasts two slow clock cycles (worst
case). Once the system reset signal is asserted, the processor and the peripherals are stopped one slow clock
cycle before the core voltage regulator shuts off and the SHDN pin is pulled down to ground.
When the embedded voltage regulator is not used and VDDCORE is supplied via an external supply, the voltage
regulator can be disabled. This is done by clearing the ONREG bit in SUPC_MR.
20.4.4 Segmented LCD Voltage Regulator Control
The SUPC can be used to select the power supply source of the Segmented LCD (SLCD) voltage regulator.
This selection is done by the LCDMODE field in SUPC_MR. After a backup reset, the LCDMODE field is at 0. No
power supply source is selected and the SLCD reset signal is asserted.
The status of the SLCD Controller (SLCDC) reset is given by the LCDS field in SUPC_ SR.
 If LCDMODE is written to 2 while it is at 0, after the write resynchronization time (about 2 slow clock cycles),
the external power supply source is selected, then after one slow clock cycle, the SLCDC reset signal is
released.
 If LCDMODE is written to 0 while it is at 2, after the write resynchronization time (about 2 slow clock cycles),
the SLCDC reset signal is asserted, then after one slow clock cycle, the external power supply source is
deselected.
398
SAM4C Series [DATASHEET]
Atmel-11102E-ATARM-SAM4C32-SAM4C16-SAM4C8-Datasheet_06-Oct-14