SAM4C_14 Datasheet, PDF (101/1303 Pages) ATMEL Corporation – Atmel | SMART ARM-based Flash MCU

ASR #n
arithmetic shift right n bits, 1 ≤ n ≤ 32.
LSL #n
logical shift left n bits, 1 ≤ n ≤ 31.
LSR #n
logical shift right n bits, 1 ≤ n ≤ 32.
ROR #n
rotate right n bits, 1 ≤ n ≤ 31.
RRX
rotate right one bit, with extend.
-
if omitted, no shift occurs, equivalent to LSL #0.
If the user omits the shift, or specifies LSL #0, the instruction uses the value in Rm.
If the user specifies a shift, the shift is applied to the value in Rm, and the resulting 32-bit value is used by the
instruction. However, the contents in the register Rm remains unchanged. Specifying a register with shift also
updates the carry flag when used with certain instructions. For information on the shift operations and how they
affect the carry flag, see “Flexible Second Operand”
12.6.3.4 Shift Operations
Register shift operations move the bits in a register left or right by a specified number of bits, the shift length.
Register shift can be performed:
 Directly by the instructions ASR, LSR, LSL, ROR, and RRX, and the result is written to a destination register
 During the calculation of Operand2 by the instructions that specify the second operand as a register with
shift. See “Flexible Second Operand” . The result is used by the instruction.
The permitted shift lengths depend on the shift type and the instruction. If the shift length is 0, no shift occurs.
Register shift operations update the carry flag except when the specified shift length is 0. The following
subsections describe the various shift operations and how they affect the carry flag. In these descriptions, Rm is
the register containing the value to be shifted, and n is the shift length.
ASR
Arithmetic shift right by n bits moves the left-hand 32-n bits of the register, Rm, to the right by n places, into the
right-hand 32-n bits of the result. And it copies the original bit[31] of the register into the left-hand n bits of the
result. See Figure 12-8.
The ASR #n operation can be used to divide the value in the register Rm by 2ⁿ, with the result being rounded
towards negative-infinity.
When the instruction is ASRS or when ASR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS,
ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the
register Rm.
 If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.
 If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of Rm.
Figure 12-8. ASR #3
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LSR
Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-
hand 32-n bits of the result. And it sets the left-hand n bits of the result to 0. See Figure 12-9.
SAM4C Series [DATASHEET]
Atmel-11102E-ATARM-SAM4C32-SAM4C16-SAM4C8-Datasheet_06-Oct-14
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