405GPR Datasheet, PDF (7/57 Pages) Applied Micro Circuits Corporation – Power PC 405GPr Embedded Processor

Revision 2.04 – September 7, 2007
Data Sheet
405GPr – Power PC 405GPr Embedded Processor
Address Map Support
The PPC405GPr incorporates two simple and separate address maps. The first address map defines the possible
use of address regions that the processor can access. The second address map is for Device Configuration
Registers (DCRs). The DCRs are accessed by software running on the PPC405GPr processor through the use of
mtdcr and mfdcr instructions.
System Memory Address Map 4GB System Memory
Function
Subfunction
Start Address
End Address
Size
0x00000000
0xE7FFFFFF
3712MB
General Use
SDRAM, External Peripherals, and PCI
Memory
Note: Any of the address ranges listed at
right may be use for any of the above
functions.
0xE8010000
0xEC000000
0xEEE00000
0xEF500000
0xE87FFFFF
0xEEBFFFFF
0xEF3FFFFF
0xEF5FFFFF
8 MB
44 MB
6 MB
1 MB
0xF0000000
0xFFFFFFFF
256 MB
Boot-up
Peripheral Bus Boot ¹
PCI Boot ²
0xFFE00000
0xFFFE0000
0xFFFFFFFF
0xFFFFFFFF
2MB
128KB
PCI I/O
0xE8000000
0xE800FFFF
64KB
PCI I/O
0xE8800000
0xEBFFFFFF
56MB
PCI
Configuration Registers
0xEEC00000
0xEEC00007
8B
Interrupt Acknowledge and Special Cycle
0xEED00000
0xEED00003
4B
Local Configuration Registers
0xEF400000
0xEF40003F
64B
UART0
0xEF600300
0xEF600307
8B
UART1
0xEF600400
0xEF600407
8B
Internal Peripherals
IIC0
OPB Arbiter
0xEF600500
0xEF60051F
32B
0xEF600600
0xEF60063F
64B
GPIO Controller Registers
0xEF600700
0xEF60077F
128B
Ethernet Controller Registers
0xEF600800
0xEF6008FF
256B
Notes:
1. When peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above.
2. If PCI boot is selected, a PLB-to-PCI mapping is automatically configured at reset to the address range listed above.
3. After the boot process, software may reassign the boot memory regions for other uses.
4. All address ranges not listed above are reserved.
AMCC
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