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405GPR Datasheet, PDF (47/57 Pages) Applied Micro Circuits Corporation – Power PC 405GPr Embedded Processor
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Revision 2.04 – September 7, 2007
Data Sheet
405GPr – Power PC 405GPr Embedded Processor
Notes: 1. In all of the following I/O Specifications tables a timing values of “na” means “not applicable” and “dc”
means “don’t care.”
2. See “Test Conditions” on page 42 for output capacitive loading.
I/O Specifications—Group 1 (Sheet 1 of 3)
Notes:
1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.
In synchronous mode, timing is relative to SysClk. In asynchronous mode, timing is relative to PCIClk.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at 2.4 V
and I/O L is specified at 0.4 V.
Signal
PCI Interface
PCIAD31:0
PCIC3:0[BE3:0]
PCIClk
PCIDevSel
PCIFrame
PCIGnt0[Req]
PCIGnt1:5
PCIIDSel
PCIINT[PerWE]
PCIIRDY
PCIParity
PCIPErr
PCIReq0[Gnt]
PCIReq1:5
PCIReset
PCISErr
PCIStop
PCITRDY
Ethernet Interface
EMCMDClk
EMCMDIO[PHYMDIO]
EMCTxD3:0
EMCTxEn
EMCTxErr
PHYCol
PHYCrS
PHYRxClk
PHYRxD3:0
PHYRxDV
PHYRxErr
PHYTxClk
Input (ns)
Setup Time Hold Time
(TIS min) (TIH min)
Output (ns)
Valid Delay Hold Time
(TOV max) (TOH min)
3
0
6
1
3
0
6
1
dc
dc
na
na
3
0
6
1
3
0
6
1
na
na
na
na
3
0
6
1
na
na
dc
dc
3
0
6
1
3
0
6
1
3
0
6
1
5
0
na
na
na
na
na
na
na
na
na
na
3
0
6
1
3
0
6
1
na
na
settable
2
100
0
1 OPB clock 1 OPB clock
period + 10ns period
na
na
20
2
na
na
20
2
na
na
20
2
4
1
na
na
4
1
na
na
4
1
na
na
Output Current (mA)
I/O H
(min)
I/O L
(min)
0.5
1.5
0.5
1.5
na
na
0.5
1.5
0.5
1.5
0.5
1.5
na
na
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
na
na
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
10.3
7.1
10.3
7.1
10.3
7.1
10.3
7.1
10.3
7.1
10.3
7.1
10.3
7.1
na
na
10.3
7.1
10.3
7.1
10.3
7.1
na
na
Clock
Notes
PCI Clock
PCI Clock
PCI Clock
PCI Clock
PCI Clock
PCI Clock
PCI Clock
PCI Clock
PCI Clock
PCI Clock
PCI Clock
PCI Clock
PCI Clock
PCI Clock
PCI Clock
1
1
async
1
1
1
1
async
1
1
1
1
1
1
2, async
EMCMDClk
2
PHYTX
PHYTX
PHYTX
PHYRX
PHYRX
PHYRX
2
2
2
2, async
2, async
2, async
2
2
2
2, async
AMCC
47
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