405GPR Datasheet, PDF (50/57 Pages) Applied Micro Circuits Corporation – Power PC 405GPr Embedded Processor

405GPr – Power PC 405GPr Embedded Processor
Revision 2.04 – September 7, 2007
Data Sheet
I/O Specifications—Group 2
Notes:
1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM.
2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
3. SDRAM interface hold times are guaranteed at the PPC405GPr package pin. System designers must use the PPC405GPr
IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections,
and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
4. PerClk timing is specified with a 10pF load at the package pin. The indicated timing is valid only if PerClk feedback is
selected. Refer to the PowerPC 405GPr Embedded Processor User’s Manual for more information.
5. Input timings are specified at 1.5V, assuming transition times between 1 and 2ns, when measured between the 10% and
90% points of the output voltage.
6. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns)
Signal
Setup Time Hold Time
(T_IS min) (T_IH min)
SDRAM Interface
BA1:0
na
na
BankSel3:0
na
na
CAS
na
na
ClkEn0:1
na
na
DQM0:3
na
na
DQMCB
na
na
ECC0:7
1.4
0
MemAddr12:0
na
na
MemData0:31
1.4
0
RAS
na
na
WE
na
na
External Slave Peripheral Interface
DMAAck0:3
na
na
DMAReq0:3
3.2
0
EOT0:3/TC0:3
dc
dc
PerAddr0:31
2.2
0
PerBLast
3.3
0
PerCS0
PerCS1:7[GPIO10:16]
na
na
PerData0:31
4.7
0.9
PerOE
na
na
PerPar0:3
2.3
0
PerR/W
3.3
0
PerReady
5.5
0
PerWBE0:3
2.3
0
External Master Peripheral Interface
BusReq
na
na
ExtAck
na
na
ExtReq
4.1
0
ExtReset
na
na
HoldAck
na
na
HoldPri
2.1
0
HoldReq
3.1
0
PerClk
na
na
PerErr
2.4
0
Output (ns)
Valid Delay Hold Time
(T_OV max) (T_OH min)
4.5
1.6
4.5
1.5
4.4
1.5
3.9
1.4
4.5
1.4
4.3
1.4
4.5
1.5
4.6
1.5
5.1
1.4
4.4
1.5
4.4
1.5
6.1
2.2
na
na
6.4
2
7.1
2
6.5
2.3
6.5
2.1
7.2
1.9
6.5
2.1
7.2
2.1
6.6
2.1
na
na
6.1
2.2
6.1
2.2
5.9
2.1
na
na
6
1
6.1
2
na
na
na
na
0.7
-0.5
na
na
Output Current (mA)
I/O H
I/O L
(minimum) (minimum)
Clock
Notes
15.3
10.2
MemClkOut 1, 2, 5
15.3
10.2
MemClkOut 2, 5
15.3
10.2
MemClkOut 1, 2, 5
23
19.3
MemClkOut 2, 5
15.3
10.2
MemClkOut 2, 5
15.3
10.2
MemClkOut 2, 5
15.3
10.2
MemClkOut 2, 5
15.3
10.2
MemClkOut 1, 2, 5
15.3
10.2
MemClkOut 2, 5
15.3
10.2
MemClkOut 1, 2, 5
15.3
10.2
MemClkOut 1, 2, 5
10.3
7.1
PerClk
5
na
na
PerClk
5
10.3
7.1
PerClk
5
15.3
10.2
PerClk
5
10.3
7.1
PerClk
5
10.3
7.1
PerClk
5
15.3
10.2
PerClk
5
10.3
7.1
PerClk
5
15.3
10.2
PerClk
5
10.3
7.1
PerClk
5
na
na
PerClk
5
10.3
7.1
PerClk
5
10.3
7.1
PerClk
5
10.3
7.1
PerClk
5
na
na
PerClk
5
15.3
10.2
PerClk
5
10.3
7.1
PerClk
5
na
na
PerClk
5
na
na
PerClk
5
15.3
10.2
SysClk
4, 5
na
na
PerClk
5
50
AMCC