405GPR Datasheet, PDF (41/57 Pages) Applied Micro Circuits Corporation – Power PC 405GPr Embedded Processor

Revision 2.04 – September 7, 2007
Data Sheet
405GPr – Power PC 405GPr Embedded Processor
DC Electrical Characteristics
Parameter
Symbol
Typical
Maximum
Unit
Active Operating Current (V_DD)–266MHz
I_DD
300
610
mA
Active Operating Current (V_DD)–333MHz
I_DD
325
690
mA
Active Operating Current (V_DD)–400MHz
I_DD
355
770
mA
Active Operating Current (OV_DD)
I_ODD
45
200
mA
PLL V_DD Input current
I_PLL
16
23
mA
Active Operating Power–266 MHz
P_DD
0.72
1.92
W
Active Operating Power–333MHz
P_DD
0.76
2.07
W
Active Operating Power–400MHz
P_DD
0.82
2.23
W
Note:
1. The maximum current and power values listed above are not guaranteed to be the highest obtainable. These values are dependent on
many factors including the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case
temperature, and the power supply voltages. Your specific application can produce significantly different results. V_DD (logic) current and
power are primarily dependent on the applications running and the use of internal chip functions (DMA, PCI, Ethernet, and so on). OV_DD
(I/O) current and power are primarily dependent on the capacitive loading, frequency, and utilization of the external buses. The following
information provides details about the conditions under which the listed values were obtained:
a. In general, the values were measured using a PPC405GPr Evaluation Board with four PCI devices, an external bus master on the
peripheral bus, and external wrap-back on the Ethernet port. For all CPU clock rates, PLB = 133.3MHz, OPB = PerClk = 66.6MHz,
PCI = SysClk = 33.3MHz.
b. Typical current and power are characterized at V_DD = +1.8V, OV_DD = +3.3V, and T_C = +36°C while running various applications
under the Linux operating system.
c. Maximum current and power are characterized at V_DD = +1.9V, OV_DD = +3.6V, and T_C = +85°C while running applications designed
to maximize CPU power consumption. An external PCI master heavily loads the PCI bus with transfers targeting SDRAM while the
internal DMA controller further increases SDRAM bus traffic.
2. AV_DD should be derived from V_DD using the following circuit:
V_DD
L1
+
AV_DD
L1 – 2.2μH SMT inductor (equivalent to MuRata
LQH3C2R2M34) or SMT chip ferrite bead (equivalent
to MuRata BLM31A700S)
C1
C2
C3
C1 – 3.3 μF SMT tantalum
AGND
C2 – 0.1μF SMT monolithic ceramic capacitor with X7R
dielectric or equivalent
GND
C3 – 0.01 μF SMT monolithic ceramic capacitor with X7R
dielectric or equivalent
AMCC
41