405GPR Datasheet, PDF (54/57 Pages) Applied Micro Circuits Corporation – Power PC 405GPr Embedded Processor

405GPr – Power PC 405GPr Embedded Processor
Revision 2.04 – September 7, 2007
Data Sheet
PPC405GPr New Mode Strapping Pin Assignments (Sheet 2 of 3)
Function
Option
Ball Strapping
PLL Feedback Divider ^{2, 3}
B14
DMAAck2
C12
DMAAck3
AF5
GPIO7[TS5]
Divide by 16
0
0
0
Divide by 1
0
0
0
Divide by 2
0
0
1
Divide by 3
0
0
1
Divide by 4
0
1
0
Divide by 5
0
1
0
Divide by 6
0
1
1
Divide by 7
0
1
1
Divide by 8
1
0
0
Divide by 9
1
0
0
Divide by 10
1
0
1
Divide by 11
1
0
1
Divide by 12
1
1
0
Divide by 13
1
1
0
Divide by 14
1
1
1
Divide by 15
1
1
1
OPB Divider from PLB ²
L25
EMCTxD1
J26
EMCTxD0
Divide by 1
0
0
Divide by 2
0
1
Divide by 3
1
0
Divide by 4
1
1
PCI Divider from PLB ^{2, 3}
D18
C20
GPIO1[TS1E] GPIO2[TS2E]
Divide by 1
0
0
Divide by 2
0
1
Divide by 3
1
0
Divide by 4
1
1
External Bus Divider from
PLB ²
K25
EMCTxErr
K23
EMCTxEn
Divide by 2
0
0
Divide by 3
0
1
Divide by 4
1
0
Divide by 5
1
1
ROM Width
AC2
UART1_Tx
AD2
UART1_RTS/
UART1_DTR
8-bit ROM
0
0
16-bit ROM
0
1
32-bit ROM
1
0
Reserved
1
1
ROM Location
U2
HoldAck
PPC405GPr Peripheral Attach
0
PPC405GPr PCI Attach
1
AC7
GPIO8[TS6]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
54
AMCC