405GPR Datasheet, PDF (48/57 Pages) Applied Micro Circuits Corporation – Power PC 405GPr Embedded Processor

405GPr – Power PC 405GPr Embedded Processor
Revision 2.04 – September 7, 2007
Data Sheet
I/O Specifications—Group 1 (Sheet 2 of 3)
Notes:
1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.
In synchronous mode, timing is relative to SysClk. In asynchronous mode, timing is relative to PCIClk.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
3. For PCI, I/O H is specified at 0.9OV_DD and I/O L is specified at 0.1OV_DD. For all other interfaces, I/O H is specified at 2.4 V
and I/O L is specified at 0.4 V.
Input (ns)
Signal
Setup Time Hold Time
(T_IS min) (T_IH min)
Internal Peripheral Interface
IICSCL
na
na
IICSDA
na
na
UART0_CTS
na
na
UART0_DCD
na
na
UART0_DSR
na
na
UART0_DTR
UART0_RI
na
na
UART0_RTS
UART0_Rx
na
na
UART0_Tx
UART1_RTS/
UART1_DTR
UART1_DSR/
UART1_CTS
na
na
UART1_Rx
na
na
UART1_Tx
UARTSerClk
na
na
Interrupts Interface
IRQ0:6[GPIO17:23]
JTAG Interface
TCK
TDI
TDO
TMS
TRST
System Interface
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO24
Halt
dc
dc
SysClk
SysErr
SysReset
TestEn
dc
dc
TmrClk
dc
dc
Output (ns)
Valid Delay Hold Time
(T_OV max) (T_OH min)
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
10
1
na
na
na
na
Output Current (mA)
I/O H
(min)
I/O L
(min)
15.3
10.2
15.3
10.2
10.3
7.1
10.3
7.1
10.3
7.1
10.3
7.1
10.3
7.1
10.3
7.1
10.3
7.1
10.3
7.1
10.3
7.1
na
na
na
na
10.3
7.1
na
na
10.3
7.1
na
na
na
na
10.3
7.1
na
na
na
na
10.3
7.1
na
na
na
na
10.3
7.1
10.3
7.1
na
na
na
na
Clock
Notes
async
async
async
async
async
async
async
async
async
async
48
AMCC