405GPR Datasheet, PDF (49/57 Pages) Applied Micro Circuits Corporation – Power PC 405GPr Embedded Processor

Revision 2.04 – September 7, 2007
Data Sheet
405GPr – Power PC 405GPr Embedded Processor
I/O Specifications—Group 1 (Sheet 3 of 3)
Notes:
1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.
In synchronous mode, timing is relative to SysClk. In asynchronous mode, timing is relative to PCIClk.
2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
3. For PCI, I/O H is specified at 0.9OV_DD and I/O L is specified at 0.1OV_DD. For all other interfaces, I/O H is specified at 2.4 V
and I/O L is specified at 0.4 V.
Signal
Trace
[TS1E]
[TS2E]
[TS1O]
[TS2O]
[TS3]
[TS4]
[TS5]
[TS6]
Input (ns)
Setup Time Hold Time
(T_IS min) (T_IH min)
Output (ns)
Valid Delay Hold Time
(T_OV max) (T_OH min)
Output Current (mA)
I/O H
(min)
I/O L
(min)
Clock
Notes
10pF load
na
na
PT_C/2+0.7 PT_C/2-0.5
10.3
7.1
TrcClk
on
clk/data
AMCC
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