405GPR Datasheet, PDF (37/57 Pages) Applied Micro Circuits Corporation – Power PC 405GPr Embedded Processor

Revision 2.04 – September 7, 2007
Data Sheet
405GPr – Power PC 405GPr Embedded Processor
Signal Functional Description (Sheet 8 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 29.
Signal Name
[TrcClk]GPIO9
Ground pins
GND
OV_DD pins
OV_DD
V_DD pins
V_DD
Other pins
Reserved
Description
I/O
Trace interface clock. A toggling signal that is always half of the CPU
core frequency. To access this function, software must toggle a DCR
bit
or
General Purpose I/O.
Note: Initialization strapping must hold this pin low (0) during reset.
O[I/O]
Type
5V tolerant
3.3V LVTTL
Ground
Note: L11-L16, M11-M16, N11-N16, P11-P16, R11-R16, and
T11-T16 are also thermal balls.
Output driver voltage—3.3V.
Logic voltage—1.8V.
Reserved—Except for AF4, do not connect signals, voltage, or
ground to these pins. AF4 must be tied to OV_DD or GND.
Notes
1, 6
AMCC
37