405GPR Datasheet, PDF (6/57 Pages) Applied Micro Circuits Corporation – Power PC 405GPr Embedded Processor

405GPr – Power PC 405GPr Embedded Processor
Revision 2.04 – September 7, 2007
Data Sheet
PPC405GPr Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
16KB
D-Cache
Clock
Control
Reset
Power
Mgmt
Timers
MMU
DOCM
IOCM
PPC405
Processor Core
JTAG
DCU
Trace
ICU
OCM
SRAM
OCM
Control
DCR Bus
DCRs
GPIO IIC UART UART
16KB _Arb
I-Cache
On-chip Peripheral Bus (OPB)
DMA
Controller
(4-Channel)
OPB
Bridge
MAL
Ethernet
Arb
Processor Local Bus (PLB)
Code
Decompression
(CodePack™)
SDRAM
Controller
13-bit addr
32-bit data
External
Bus
Controller
External
Bus Master
Controller
32-bit addr
32-bit data
PCI Bridge
66 MHz max (async)
MII
33 MHz max (sync)
The PPC405GPr is designed using the IBM^® Microelectronics Blue Logic^TM methodology in which major functional
blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent
way to create complex ASICs using IBM CoreConnect^TM Bus Architecture.
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AMCC