405GPR Datasheet, PDF (33/57 Pages) Applied Micro Circuits Corporation – Power PC 405GPr Embedded Processor

Revision 2.04 – September 7, 2007
Data Sheet
405GPr – Power PC 405GPr Embedded Processor
Signal Functional Description (Sheet 4 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 29.
Signal Name
PerCS0
PerCS1:7[GPIO10:16]
PerOE
PerR/W
PerReady
PerBLast
DMAReq0:3
DMAAck0:3
EOT0:3/TC0:3
Description
I/O
Peripheral chip select bank 0.
O
Seven additional peripheral chip selects
or
General Purpose I/O. To access this function, software must toggle a
DCR bit.
O[I/O]
Used by either the peripheral controller or the DMA controller
depending upon the type of transfer involved. When the PPC405GPr O
is the bus master, it enables the selected device to drive the bus.
Used by the PPC405GPr when not in external master mode, as
output by either the peripheral controller or DMA controller depending
upon the type of transfer involved. High indicates a read from
memory, low indicates a write to memory.
I/O
Otherwise it used by the external master as an input to indicate the
direction of data transfer.
Used by a peripheral slave to indicate it is ready to transfer data.
I
Used by the PPC405GPr when not in external master mode,
otherwise used by external master. Indicates the last transfer of a
I/O
memory access.
DMAReq0:3 are used by slave peripherals to indicate they are
prepared to transfer data.
I
DMAAck0:3 are used by the PPC405GPr to cause the DMA
peripheral to transfer data.
O
End Of Transfer/Terminal Count.
I/O
Type
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
Notes
7
1, 7
7
1
1
1, 7
1
6
1
AMCC
33