405GPR Datasheet, PDF (36/57 Pages) Applied Micro Circuits Corporation – Power PC 405GPr Embedded Processor

405GPr – Power PC 405GPr Embedded Processor
Revision 2.04 – September 7, 2007
Data Sheet
Signal Functional Description (Sheet 7 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 29.
Signal Name
GPIO1[TS1E]
GPIO2[TS2E]
GPIO3[TS1O]
GPIO4[TS2O]
GPIO5:8[TS3:6]
GPIO9[TrcClk]
GPIO24
TestEn
TmrClk
Trace Interface
[TS1E]GPIO1
[TS2E]GPIO2
[TS1O]GPIO3
[TS2O]GPIO4
[TS3:6]GPIO5:8
Description
I/O
General Purpose I/O
or
Even Trace execution status. To access this function, software must
toggle a DCR bit.
I/O[O]
General Purpose I/O
or
Odd Trace execution status. To access this function, software must
toggle a DCR bit.
I/O[O]
General Purpose I/O
or
Odd Trace execution status. To access this function, software must
toggle a DCR bit.
I/O[O]
General Purpose I/O
or
Trace status. To access this function, software must toggle a DCR
bit.
I/O[O]
General Purpose I/O
or
Trace interface clock. A toggling signal that is always half of the CPU
core frequency. To access this function, software must toggle a DCR
bit.
Note: Initialization strapping must hold this pin low (0) during reset.
I/O[O]
General Purpose I/O.
Note: The pull-up initialization strapping resistor must be 1kΩ rather ^I/O
than 3kΩ in order to overcome the internal pull-down resistor.
Test Enable. Used only for manufacturing tests. Pull down for normal
operation.
I
An external clock input that can be used to clock the timers in the
CPU core.
I
Type
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
3.3V LVTTL
w/pull-down
1.8V CMOS
w/pull-down
5V tolerant
3.3V LVTTL
Even Trace execution status. To access this function, software must
toggle a DCR bit
or
General Purpose I/O.
O[I/O]
Odd Trace execution status. To access this function, software must
toggle a DCR bit
or
General Purpose I/O.
O[I/O]
Odd Trace execution status. To access this function, software must
toggle a DCR bit
or
General Purpose I/O.
O[I/O]
Trace status. To access this function, software must toggle a DCR bit
or
O[I/O]
General Purpose I/O.
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
5V tolerant
3.3V LVTTL
Notes
1, 6
1, 6
1, 6
1, 6
1, 6
1, 6
1
1, 6
1, 6
1, 6
1, 6
36
AMCC