EP2AGZ225HF40I3N Datasheet, PDF (94/382 Pages) Altera Corporation – Volume 1: Device Interfaces and Integration

4–18
Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
Double Multiplier
You can configure the Arria II DSP block to support an unsigned 54 × 54-bit multiplier
that is required to compute the mantissa portion of an IEEE double precision floating
point multiplication. You can build a 54 × 54-bit multiplier with basic 18 × 18
multipliers, shifters, and adders. To efficiently use built-in shifters and adders in the
Arria II DSP block, a special double mode (partial 54 × 54 multiplier) is available that
is a slight modification to the basic 36 × 36 multiplier mode, as shown in Figure 4–11
and Figure 4–12.
Figure 4–11. Double Mode Shown for a Half DSP Block
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
dataa_0[35..18]
datab_0[35..18]
+
dataa_0[17..0]
datab_0[35..18]
dataa_0[35..18]
datab_0[17..0]
+
dataa_0[17..0]
datab_0[17..0]
Half-DSP Block
72
+
result[ ]
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010 Altera Corporation