EP2AGZ225HF40I3N Datasheet, PDF (13/382 Pages) Altera Corporation – Volume 1: Device Interfaces and Integration

Section I. Device Core for Arria II Devices
This section provides a complete overview of all features relating to the Arria^® II
device family, the industry’s first cost-optimized 40 nm FPGA family. This section
includes the following chapters:
■ Chapter 1, Overview for the Arria II Device Family
■ Chapter 2, Logic Array Blocks and Adaptive Logic Modules in Arria II Devices
■ Chapter 3, Memory Blocks in Arria II Devices
■ Chapter 4, DSP Blocks in Arria II Devices
■ Chapter 5, Clock Networks and PLLs in Arria II Devices
Revision History
Refer to each chapter for its own specific revision history. For information on when
each chapter was updated, refer to the Chapter Revision Dates section, which appears
in this volume.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration