EP2AGZ225HF40I3N Datasheet, PDF (11/382 Pages) Altera Corporation – Volume 1: Device Interfaces and Integration

Chapter Revision Dates
The chapters in this document, Arria II Device Handbook Volume 1: Device Interfaces
and Integration, were revised on the following dates. Where chapters or groups of
chapters are available separately, part numbers are listed.
Chapter 1.
Overview for the Arria II Device Family
Revised:
July 2012
Part Number: AIIGX51001-4.4
Chapter 2.
Logic Array Blocks and Adaptive Logic Modules in Arria II Devices
Revised:
December 2010
Part Number: AIIGX51002-2.0
Chapter 3.
Memory Blocks in Arria II Devices
Revised:
December 2011
Part Number: AIIGX51003-3.2
Chapter 4.
DSP Blocks in Arria II Devices
Revised:
December 2010
Part Number: AIIGX51004-4.0
Chapter 5.
Clock Networks and PLLs in Arria II Devices
Revised:
July 2012
Part Number: AIIGX51005-4.2
Chapter 6.
I/O Features in Arria II Devices
Revised:
December 2011
Part Number: AIIGX51006-4.2
Chapter 7.
External Memory Interfaces in Arria II Devices
Revised:
June 2011
Part Number: AIIGX51007-4.1
Chapter 8.
High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Revised:
July 2012
Part Number: AIIGX51008-4.3
Chapter 9.
Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Revised:
July 2012
Part Number: AIIGX51009-4.3
Chapter 10. SEU Mitigation in Arria II Devices
Revised:
July 2012
Part Number: AIIGX51010-4.2
Chapter 11. JTAG Boundary-Scan Testing in Arria II Devices
Revised:
December 2010
Part Number: AIIGX51011-4.0
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration