EP2AGZ225HF40I3N Datasheet, PDF (242/382 Pages) Altera Corporation – Volume 1: Device Interfaces and Integration

7–38
Chapter 7: External Memory Interfaces in Arria II Devices
Arria II External Memory Interface Features
Figure 7–25 shows the registers available in the Arria II GX input path. The input path
consists of DDR input registers and resynchronization registers. You can bypass each
block of the input path.
Figure 7–25. IOE Input Registers for Arria II GX Devices (Note 1)
Double Data Rate Input Registers
DQ
datain
D
Q
regouthi
Synchronization Registers
D
Q
To Core (rdata0)
Differential
DQS (2), (4) ^Input
Buffer
DFF
Input Reg A _I
D
Q ^neg_reg_out D
regoutlo
Q
DFF
Input Reg BI
DFF
Input Reg CI
DFF
D
Q
DFF
To Core (rdata1)
DQSn
CQn (3)
1
Resynchronization
Clock
0
(resync_clk_2x)
(3)
Notes to Figure 7–25:
(1) You can bypass each register block in this path.
(2) The input clock can be from the DQS logic block (whether the postamble circuitry is bypassed or not) or from a global clock line.
(3) This input clock comes from the CQn logic block.
(4) The DQS signal must be inverted for DDR interfaces except for the QDR II+/QDR II SRAM interfaces. This inversion is done automatically if you
use the Altera external memory interface IPs.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
June 2011 Altera Corporation