EP2AGZ225HF40I3N Datasheet, PDF (122/382 Pages) Altera Corporation – Volume 1: Device Interfaces and Integration

5–14
Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
Clock Output Connections
PLLs in Arria II GX devices can drive up to 24 RCLK networks and eight GCLK
networks, while PLLs in Arria II GZ devices can drive up to 20 RCLK networks and
four GCLK networks. The Quartus II software automatically assigns PLL clock
outputs to RCLK or GCLK networks.
Table 5–8 and Table 5–9 list the Arria II PLL connectivity to GCLK networks.
Table 5–8. PLL Connectivity to GCLKs for Arria II GX Devices
Clock Network
PLL Number
1
2
3
4
5
6
GCLK[0..3]
GCLK[4..7]
GCLK[8..11]
GCLK[12..15]
v
—
—
v
—
—
—
—
v
v
—
—
—
v
v
—
v
v
v
v
—
—
—
—
Table 5–9. PLL Connectivity to the GCLK Networks for Arria II GZ Devices (Note 1)
Clock Network
PLL Number
L2
L3
B1
B2
R2
R3
T1
T2
GCLK[0..3]
v
v—
—
—
—
—
—
GCLK[4..7]
—
—
v
v
—
—
—
—
GCLK[8..11]
—
—
—
—
v
v
—
—
GCLK[12..15]
—
—
—
—
—
—
v
v
Note to Table 5–9:
(1) Only PLL counter outputs C0 - C3 can drive the GCLK networks.
Table 5–10 and Table 5–11 list how the PLL clock outputs connect to RCLK networks.
Table 5–10. RCLK Outputs from PLLs for Arria II GX Devices
Clock Resource
PLL Number
1
2
3
4
5
6
RCLK[0..11]
RCLK[12..23]
RCLK[24..35]
RCLK[36..47]
v
—
—
v
—
—
—
—
v
v
—
—
—
v
v
—
v
v
v
v
—
—
—
—
Table 5–11. RCLK Outputs From the PLL Clock Outputs for Arria II GZ Device (Part 1 of 2)
Clock Resource
PLL Number
L2
L3
B1 B2
R2 R3
T1
T2
RCLK[0..11]
RCLK[12..31]
v
v
—
—
—
—
—
—
—
—vv
—
—
—
—
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation