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EP2AGZ225HF40I3N Datasheet, PDF (225/382 Pages) Altera Corporation – Volume 1: Device Interfaces and Integration | |||
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Chapter 7: External Memory Interfaces in Arria II Devices
Combining Ã16/Ã18 DQ/DQS Groups for Ã36 QDR II+/QDR II SRAM Interface
7â21
Using the RUP and RDN Pins in a DQ/DQS Group Used for Memory Interfaces
in Arria II GZ Devices
You can use the DQS/DQSn pins in some of the Ã4 groups as RUP and RDN pins (listed
in the pin table). You cannot use a Ã4 DQ/DQS group for memory interfaces if any of
its pin members are used as RUP and RDN pins for OCT calibration. You may be able to
use the Ã8/Ã9 group that includes this Ã4 DQ/DQS group, if either of the following
applies:
â You are not using DM pins with your differential DQS pins
â You are not using complementary or differential DQS pins
You can use the Ã8/Ã9 group because a DQ/DQS Ã8/Ã9 group actually comprises 12
pins, because the groups are formed by stitching two DQ/DQS groups in Ã4 mode
with six pins each (refer to Table 7â1 on page 7â5). A typical Ã8 memory interface
consists of one DQS, one DM, and eight DQ pins that add up to 10 pins. If you choose
your pin assignment carefully, you can use the two extra pins for RUP and RDN. In a
DDR3 SDRAM interface, you must use differential DQS, which means that you only
have one extra pin. In this case, pick different pin locations for the RUP and RDN pins
(for example, in the bank that contains the address and command pins).
You cannot use the RUP and RDN pins shared with DQ/DQS group pins when using
Ã9 QDR II+/QDR II SRAM devices, because the RUP and RDN pins are dual purpose
with the CQn pins. In this case, pick different pin locations for RUP and RDN pins to
avoid conflict with memory interface pin placement. You have the choice of placing
the RUP and RDN pins in the data-write group or in the same bank as the address and
command pins.
There is no restriction on using Ã16/Ã18 or Ã32/Ã36 DQ/DQS groups that include the
Ã4 groups whose pins are being used as RUP and RDN pins, because there are enough
extra pins that can be used as DQS pins.
1 For Ã8, Ã16/Ã18, or Ã32/Ã36 DQ/DQS groups whose members are used for RUP and
RDN, you must assign DQS and DQ pins manually. The Quartus® II software might
not be able to place DQS and DQ pins without manual pin assignments, resulting in a
âno-fitâ.
Combining Ã16/Ã18 DQ/DQS Groups for Ã36 QDR II+/QDR II SRAM
Interface
This implementation combines Ã16/Ã18 DQ/DQS groups to interface with a Ã36
QDR II+/QDR II SRAM device. The Ã36 read data bus uses two Ã16/Ã18 groups, and
the Ã36 write data uses another two Ã16/Ã18 or four Ã8/Ã9 groups. The CQ/CQn
signal traces are split on the board trace to connect to two pairs of CQ/CQn pins in
the FPGA. This is the only connection on the board that you must change for this
implementation. Other QDR II+/QDR II SRAM interface rules for Arria II devices
also apply for this implementation.
1 The ALTMEMPHY megafunction and UniPHY IP core do not use the QVLD signal, so
you can leave the QVLD signal unconnected as in any QDR II+/QDR II SRAM
interfaces in Arria II devices.
June 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration
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