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EP2AGZ225HF40I3N Datasheet, PDF (226/382 Pages) Altera Corporation – Volume 1: Device Interfaces and Integration | |||
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Chapter 7: External Memory Interfaces in Arria II Devices
Combining Ã16/Ã18 DQ/DQS Groups for Ã36 QDR II+/QDR II SRAM Interface
f For more information about the ALTMEMPHY megafunction and UniPHY IP core,
refer to the External Memory Interface Handbook.
1 Use one side of the device with the Ã36 mode emulation interface whenever possible,
even though the Ã36 group formed by a combination of DQ/DQS groups from the top
and bottom I/O banks, or top/bottom I/O bank and left/right I/O banks is
supported.
Rules to Combine Groups
In 572-, 780-, 1152-, and some 1517-pin package devices, there is at most one Ã16/Ã18
group per I/O bank. You can combine two Ã16/Ã18 groups from a single side of the
device for a Ã36 interface. 358-pin package devices have only one Ã16/Ã18 group in
each bank 4A and 7A. You can only form a Ã36 interface with these two banks.
For devices that do not have four Ã16/Ã18 groups in a single side of the device to
form two Ã36 groups for read and write data, you can form one Ã36 group on one side
of the device and another Ã36 group on the other side of the device. Altera
recommends forming two Ã36 groups on column I/O banks (top and bottom) only,
although forming a Ã36 group from column I/O banks and another Ã36 group from
row I/O banks for the read and write data buses is supported. For vertical migration
with the Ã36 emulation implementation, you must check if migration is possible by
enabling device migration in the Quartus II project. The Quartus II software also
supports the use of four Ã8/Ã9 DQ groups for write data pins and the migration of
these groups across device density. 358-pin package devices can only form a Ã36
group for write data pin with four Ã8/Ã9 groups.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
June 2011 Altera Corporation
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