EP2AGZ225HF40I3N Datasheet, PDF (245/382 Pages) Altera Corporation – Volume 1: Device Interfaces and Integration

Chapter 7: External Memory Interfaces in Arria II Devices
Arria II External Memory Interface Features
7–41
For Arria II GX devices, the output path is designed to route combinatorial or
registered single data rate (SDR) outputs and DDR outputs from the FPGA core.
The output enable path has a structure similar to the output path. You can have a
combinatorial or registered output in SDR applications.
Figure 7–28 shows the registers available in the Arria II GZ output and output-enable
paths. The path is divided into the HDR block, resynchronization registers, and
output and output-enable registers. The device can bypass each block of the output
and output-enable path.
Figure 7–28. IOE Output and Output-Enable Path Registers for Arria II GZ Devices (Note 1)
From Core (2)
From Core (2)
Half Data Rate to Single Data Rate
Output-Enable Registers
DQ
DFF
0
1
DQ
DFF
DQ
DFF
Double Data Rate
Output-Enable Registers
DQ
DFF
OE Reg A _OE
1
0
OR2
From Core
(wdata2) (2)
From Core
(wdata0) (2)
From Core
(wdata3) (2)
From Core
(wdata1) (2)
Half Data Rate to Single Data Rate
Output Registers
DQ
DFF
DQ
DFF
0
1
DQ
DFF
DQ
DFF
DQ
DFF
0
1
DQ
DFF
DQ
DFF
OE Reg B OE
DQ
Double Data Rate
Output Registers
DFF
1
Output Reg Ao
0
TRI
DQ or DQS
DQ
DFF
Output Reg Bo
Half-Rate Clock (3)
Write
Clock (4)
Notes to Figure 7–28:
(1) You can bypass each register block of the output and output-enable paths.
(2) Data coming from the FPGA core are at half the frequency of the memory interface clock frequency in half-rate mode.
(3) The half-rate clock comes from the PLL.
(4) The write clock comes from the PLL. The DQ write clock and DQS write clock have a 90° offset between them.
June 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration