EP2AGZ225HF40I3N Datasheet, PDF (234/382 Pages) Altera Corporation – Volume 1: Device Interfaces and Integration

7–30
Chapter 7: External Memory Interfaces in Arria II Devices
Arria II External Memory Interface Features
Table 7–8. DLL Reference Clock Input for EP2AGZ225, EP2AGZ300, and EP2AGZ350 Devices in the 1152-Pin FineLine
BGA Package (Part 2 of 2)
DLL
CLKIN (Top/Bottom) CLKIN (Left/Right) PLL (Top/Bottom) PLL (Left/Right) PLL (Corner)
CLK4P
CLK5P
CLK10P
DLL2
PLL_B2
—
—
CLK6P
CLK11P
CLK7P
CLK12P
CLK13P
CLK10P
DLL3
PLL_T2
PLL_R2
—
CLK14P
CLK11P
CLK15P
Table 7–9. DLL Reference Clock Input for EP2AGZ225, EP2AGZ300, and EP2AGZ350 Devices in the 1517-Pin FineLine
BGA Package
DLL
DLL0
DLL1
DLL2
DLL3
CLKIN (Top/Bottom)
CLK12P
CLK13P
CLK14P
CLK15P
CLK4P
CLK5P
CLK6P
CLK7P
CLK4P
CLK5P
CLK6P
CLK7P
CLK12P
CLK13P
CLK14P
CLK15P
CLKIN (Left/Right)
CLK0P
CLK1P
CLK2P
CLK3P
CLK0P
CLK1P
CLK2P
CLK3P
CLK8P
CLK9P
CLK10P
CLK11P
CLK8P
CLK9P
CLK10P
CLK11P
PLL (Top/Bottom)
PLL_T1
PLL_B1
PLL_B2
PLL_T2
PLL (Left/Right)
PLL_L2
PLL_L3
PLL_R3
PLL_R2
PLL (Corner)
—
—
—
—
1 If you use the ALTMEMPHY megafunction or UniPHY IP core, Altera recommends
using the dedicated PLL input pin for the PLL reference clock.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
June 2011 Altera Corporation