EP2AGZ225HF40I3N Datasheet, PDF (87/382 Pages) Altera Corporation – Volume 1: Device Interfaces and Integration

Chapter 4: DSP Blocks in Arria II Devices
DSP Block Resource Descriptions
4–11
Multiplier and First-Stage Adder
The multiplier stage supports 9 × 9, 12 × 12, 18 × 18, or 36 × 36 multipliers. Other
word lengths are padded up to the nearest appropriate native wordlength; for
example, 16 × 16 is padded up to use 18 × 18. For more information, refer to
“Independent Multiplier Modes” on page 4–14. Depending on the data width of the
multiplier, a single DSP block can perform many multiplications in parallel.
Each multiplier operand can be a unique signed or unsigned number. Two dynamic
signals, signa and signb, control the representation of each operand, respectively. A
logic 1 value on the signa/signb signal indicates that data A/data B is a signed
number; a logic 0 value indicates an unsigned number.
Table 4–4 lists the sign of the multiplication result for the various operand sign
representations. If any one of the operands is a signed value, the result of the
multiplication is signed.
Table 4–4. Multiplier Sign Representation for Arria II Devices
Data A (signa Value)
Data B (signb Value)
Unsigned (logic 0)
Unsigned (logic 0)
Signed (logic 1)
Signed (logic 1)
Unsigned (logic 0)
Signed (logic 1)
Unsigned (logic 0)
Signed (logic 1)
Result
Unsigned
Signed
Signed
Signed
Each half block has its own signa and signb signal. Therefore, all data A inputs
feeding the same half-DSP block must have the same sign representation. Similarly, all
data B inputs feeding the same half-DSP block must have the same sign
representation. The multiplier offers full precision regardless of the sign
representation in all operational modes except for full precision 18 × 18 loopback and
two-multiplier adder modes. For more information, refer to “Two-Multiplier Adder
Sum Mode” on page 4–20.
1 By default, when the signa and signb signals are unused, the Quartus II software sets
the multiplier to perform unsigned multiplication.
Figure 4–5 on page 4–8 shows that the outputs of the multipliers are the only outputs
that can feed into the first-stage adder. There are four first-stage adders in a DSP block
(two adders per half-DSP block). The first-stage adder block has the ability to perform
addition and subtraction. The control signal for addition or subtraction is static and
you must configure after compilation. The first-stage adders are used by the sum
modes to compute the sum of two multipliers, 18 × 18-complex multipliers, and to
perform the first stage of a 36 × 36 multiply and shift operation.
Depending on your specifications, the output of the first-stage adder has the option to
feed into the pipeline registers, second-stage adder, rounding and saturation unit, or
the output registers.
December 2010 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration