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EP3C120F484C7 Datasheet, PDF (90/274 Pages) Altera Corporation – Cyclone III Device Handbook | |||
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5â30
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
PLL Reconfiguration
Figure 5â23 shows the scan chain bit order sequence for one PLL post-scale counter in
Cyclone III device family PLLs.
Figure 5â23. Scan Chain Bit Order
HB
HB
HB
HB
HB
HB
HB
HB
HB
HB
0
1
2
3
4
5
6
7
8
9
rbypass
DATAIN
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
DATAOUT
0
1
2
3
4
5
6
7
8
9
rselodd
f For more information about the PLL scan chain, refer to the Implementing PLL
Reconfiguration in Cyclone III Devices application note.
Charge Pump and Loop Filter
You can reconfigure the charge pump and loop filter settings to update the PLL
bandwidth in real time. Table 5â5 through Table 5â7 list the possible settings for
charge pump (ICP), loop filter resistor (R), and capacitor (C) values for Cyclone III
device family PLLs.
Table 5â5. Charge Pump Bit Control
CP[2]
0
0
0
1
CP[1]
0
0
1
1
CP[0]
0
1
1
1
Setting (Decimal)
0
1
3
7
Table 5â6. Loop Filter Resistor Value Control
LFR[4]
LFR[3]
LFR[2]
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
0
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
LFR[1]
0
1
0
0
0
1
0
0
1
0
1
LFR[0]
0
1
0
0
0
1
0
0
1
0
0
Setting
(Decimal)
0
3
4
8
16
19
20
24
27
28
30
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
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