EP3C120F484C7 Datasheet, PDF (115/274 Pages) Altera Corporation – Cyclone III Device Handbook

Chapter 6: I/O Features in the Cyclone III Device Family
I/O Banks
6–17
Table 6–5 lists the I/O standards supported when a pin is used as a regular I/O pin in
the I/O banks of the Cyclone III device family.
Table 6–5. Cyclone III Device Family I/O Standards Support
I/O Standard
I/O Banks
1
2
3
4
5
6
7
8
3.3-V LVTTL/LVCMOS,
3.0-V LVTTL/LVCMOS,
2.5-V LVTTL/LVCMOS,
1.8-V LVTTL/LVCMOS,
1.5-V LVCMOS,
1.2V LVCMOS,
3.0-V PCI/PCI-X
v
v
v
v
v
v
v
v
SSTL-18 Class I/II,
SSTL-2 Class I/II,
HSTL-18 Class I/II,
HSTL-15 Class I/II,
HSTL-12 Class I
v
v
v
v
v
v
v
v
HSTL-12 Class II
—
—
v
v
—
—
v
v
Differential SSTL-2,
Differential SSTL-18,
Differential HSTL-18,
Differential HSTL-15,
Differential HSTL-12
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
PPDS ^{(2), (3)}
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
LVDS ⁽²⁾
v
v
v
v
v
v
v
v
BLVDS
RSDS and mini-LVDS ⁽²⁾
v
v
v
v
v
v
v
v
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
Differential LVPECL
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
Notes to Table 6–5:
(1) These differential I/O standards are supported only for clock inputs and dedicated PLL_OUT outputs.
(2) True differential (PPDS, LVDS, mini-LVDS, and RSDS I/O standards) outputs are supported in row I/O banks only. Differential outputs in
column I/O banks require an external resistors network.
(3) This I/O standard is supported for outputs only.
(4) This I/O standard is supported for clock inputs only.
Each I/O bank of the Cyclone III device family has a VREF bus to accommodate
voltage-referenced I/O standards. Each VREF pin is the reference source for its V_REF
group. If you use a V_REF group for voltage-referenced I/O standards, connect the VREF
pin for that group to the appropriate voltage level. If you do not use all the V_REF
groups in the I/O bank for voltage referenced I/O standards, you can use the VREF pin
in the unused voltage referenced groups as regular I/O pins. For example, if you have
SSTL-2 Class I input pins in I/O bank 1 and they are all placed in the VREFB1N0
group, VREFB1N0 must be powered with 1.25 V, and the remaining VREFB1N[1:3] pins
(if available) are used as I/O pins. If multiple V_REF groups are used in the same I/O
bank, the VREF pins must all be powered by the same voltage level because the VREF
pins are shorted together within the same I/O bank.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1