|
EP3C120F484C7 Datasheet, PDF (89/274 Pages) Altera Corporation – Cyclone III Device Handbook | |||
|
◁ |
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
PLL Reconfiguration
5â29
â High time count = 2 cycles
â Low time count = 1 cycle
â rselodd = 1 effectively equals:
â High time count = 1.5 cycles
â Low time count = 1.5 cycles
â Duty cycle = (1.5/3)% high time count and (1.5/3)% low time count
Scan Chain Description
Cyclone III device family PLLs have a 144-bit scan chain.
Table 5â4 lists the number of bits for each component of the PLL.
Table 5â4. Cyclone III Device Family PLL Reprogramming Bits
Block Name
Counter
Number of Bits
Other
Total
C4 (1)
16
2 (2)
18
C3
16
2 (2)
18
C2
16
2 (2)
18
C1
16
2 (2)
18
C0
16
2 (2)
18
M
16
2 (2)
18
N
16
2 (2)
18
Charge Pump
9
0
9
Loop Filter (3)
9
0
9
Total number of bits:
144
Notes to Table 5â4:
(1) LSB bit for C4 low-count value is the first bit shifted into the scan chain.
(2) These two control bits include rbypass, for bypassing the counter, and rselodd, to select the output clock duty
cycle.
(3) MSB bit for loop filter is the last bit shifted into the scan chain.
Figure 5â22 shows the scan chain order of the PLL components.
Figure 5â22. PLL Component Scan Chain Order
DATAIN
LF CP
MSB
LSB
N
M
C0
DATAOUT
C4
C3
C2
C1
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
|
▷ |