EP3C120F484C7 Datasheet, PDF (43/274 Pages) Altera Corporation – Cyclone III Device Handbook

Chapter 3: Memory Blocks in the Cyclone III Device Family
3–9
Memory Modes
Figure 3–8 shows timing waveforms for read and write operations in single-port
mode with unregistered outputs. Registering the outputs of the RAM simply delays
the q output by one clock cycle.
Figure 3–8. Cyclone III Device Family Single-Port Mode Timing Waveforms
clk_a
wren_a
rden_a
address_a
data_a
q_a (old data)
q_a (new data)
a0
a1
A
B
C
D
E
F
a0(old data)
A
B
a1(old data)
D
E
A
B
C
D
E
F
Simple Dual-Port Mode
Simple dual-port mode supports simultaneous read and write operations to different
locations. Figure 3–9 shows the simple dual-port memory configuration.
Figure 3–9. Cyclone III Device Family Simple Dual-Port Memory ⁽¹⁾
data[ ]
wraddress[ ]
wren
byteena[]
wr_addressstall
wrclock
wrclocken
aclr
rdaddress[ ]
rden
q[ ]
rd_addressstall
rdclock
rdclocken
Note to Figure 3–9:
(1) Simple dual-port RAM supports input or output clock mode in addition to the read or write clock mode shown.
Cyclone III device family M9K memory blocks support mixed-width configurations,
allowing different read and write port widths.
Table 3–3 lists mixed-width configurations.
Table 3–3. Cyclone III Device Family M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 1 of 2)
Read Port
8192 × 1
4096 × 2
2048 × 4
1024 × 8
8192 × 1
v
v
v
v
4096 × 2
v
v
v
v
2048 × 4
v
v
v
v
Write Port
1024 × 8
v
v
v
v
512 × 16
v
v
v
v
256 × 32
v
v
v
v
1024 × 9
—
—
—
—
512 × 18
—
—
—
—
256 × 36
—
—
—
—
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1