EP3C120F484C7 Datasheet, PDF (201/274 Pages) Altera Corporation – Cyclone III Device Handbook

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
9–43
You can perform the FPP configuration of Cyclone III device family with an intelligent
host, such as a MAX II device or microprocessor with flash memory. If your system
already contains a CFI flash memory, you can use it for the Cyclone III device family
configuration storage as well. The MAX II PFL feature in MAX II devices provides an
efficient method to program CFI flash memory devices through the JTAG interface
and the logic to control configuration from the flash memory device to the Cyclone III
device family. Both PS and FPP configuration schemes are supported using this PFL
feature.
f For more information about the PFL, refer to Parallel Flash Loader Megafunction User
Guide.
1 Cyclone III device family does not support enhanced configuration devices for PS or
FPP configurations.
1 FPP configuration is not supported in the E144 package of Cyclone III devices.
FPP Configuration Using an External Host
The FPP configuration using an external host provides a fast method to configure
Cyclone III device family. In the FPP configuration scheme, you can use an external
host device to control the transfer of configuration data from a storage device, such as
flash memory, to the target Cyclone III device family. You can store configuration data
in either an .rbf, .hex, or .ttf format. When using the external host, a design that
controls the configuration process, such as fetching the data from flash memory and
sending it to the device, must be stored in the external host device. Figure 9–20 shows
the configuration interface connections between the Cyclone III device family and an
external device for single-device configuration.
Figure 9–20. Single-Device FPP Configuration Using an External Host
Memory
ADDR DATA[7..0]
External Host
(MAX II Device or
Microprocessor)
VCCIO(1) VCCIO(1) _{Cyclone III Device Family}
10 k 10 k
GND
MSEL[3..0]
(3)
CONF_DONE
nSTATUS
nCE
nCEO N.C. (2)
DATA[7..0] (4)
nCONFIG
DCLK (4)
Notes to Figure 9–20:
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the device. V_CC must be high
enough to meet the V_IH specification of the I/O on the device and the external host.
(2) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0],
refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to V_CCA or GND.
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[7..0] and DCLK must fit the maximum overshoot
equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
After nSTATUS is released, the device is ready to receive configuration data and the
configuration stage begins. When nSTATUS is pulled high, the external host device
places the configuration data one byte at a time on the DATA[7..0]pins.
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1