EP3C120F484C7 Datasheet, PDF (194/274 Pages) Altera Corporation – Cyclone III Device Handbook

9–36
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
To ensure DCLK and DATA[0] are not left floating at the end of configuration, the MAX
II device must drive them either high or low, whichever is convenient on your board.
The DATA[0] pin is available as a user I/O pin after configuration. In the PS scheme,
the DATA[0] pin is tri-stated by default in user mode and must be driven by the
external host device. To change this default option in the Quartus II software, select
the Dual-Purpose Pins tab of the Device and Pin Options dialog box.
The configuration clock (DCLK) speed must be below the specified system frequency to
ensure correct configuration (Figure 9–19 on page 9–42). No maximum DCLK period
exists, which means you can pause configuration by halting DCLK for an indefinite
amount of time.
If a configuration error occurs during configuration and the Auto-restart
configuration after error option is turned on, the Cyclone III device family releases
nSTATUS after a reset time-out period (a maximum of 230 s). After nSTATUS is released
and pulled high by a pull-up resistor, the external host device tries to reconfigure the
target device without needing to pulse nCONFIG low. If this option is turned off, the
external host device must generate a low-to-high transition (with a low pulse of at
least 500 ns) on nCONFIG to restart the configuration process.
The external host device can also monitor the CONF_DONE and INIT_DONE pins to ensure
successful configuration. The CONF_DONE pin must be monitored by the external device
to detect errors and to determine when the programming is complete. If all
configuration data is sent, but CONF_DONE or INIT_DONE has not gone high, the external
device must reconfigure the target device.
Figure 9–15 shows how to configure multiple devices using an external host device.
This circuit is similar to the PS configuration circuit for a single device, except that the
Cyclone III device family is cascaded for multi-device configuration.
Figure 9–15. Multi-Device PS Configuration Using an External Host
Memory
VCCIO ₍₁₎ VCCIO _{(1) Cyclone III Device Family 1}
ADDR DATA[0]
10 k 10 k
(4)
MSEL[3..0]
External Host
(MAX II Device or
Microprocessor)
GND
CONF_DONE
nSTATUS
nCE
nCEO
DATA[0] (5)
nCONFIG
DCLK (5)
VCCIO ₍₂₎
Cyclone III Device Family 2
10 k
MSEL[3..0]
(4)
CONF_DONE
nSTATUS
nCE
nCEO
N.C. (3)
DATA[0] (5)
nCONFIG
DCLK (5)
Buffers (5)
Notes to Figure 9–15:
(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the
chain. V_CC must be high enough to meet the V_IH specification of the I/O on the device and the external host.
(2) Connect the pull-up resistor to the V_CCIO supply voltage of the I/O bank in which the nCE pin resides.
(3) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0],
refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to V_CCA or ground.
(5) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[0] and DCLK must fit the maximum overshoot
equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation