EP3C120F484C7 Datasheet, PDF (185/274 Pages) Altera Corporation – Cyclone III Device Handbook

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
9–27
1 There are no series resistors required in the AP configuration mode for Cyclone III
devices when using the Micron flash at 2.5-, 3.0-, and 3.3-V I/O standard. The output
buffer of the Micron P30 IBIS model does not overshoot above 4.1 V. Thus, series
resistors are not required for the 2.5-, 3.0-, and 3.3-V AP configuration option.
However, if there are any other devices sharing the same flash I/Os with Cyclone III
devices, all shared pins are still subject to the 4.1-V limit and may require series
resistors.
The default read mode of the supported parallel flash memory and all writes to the
parallel flash memory are asynchronous. Both the parallel flash families support a
synchronous read mode, with data supplied on the positive edge of DCLK.
■ nRESET is an active-low hard reset
■ FLASH_nCE is an active-low chip enable
■ nOE is an active-low output enable for the DATA[15..0] bus and WAIT pin
■ nAVD is an active-low address valid signal and is used to write addresses into the
flash
■ nWE is an active-low write enable and is used to write data into the flash
■ PADD[23..0] bus is the address bus supplied to the flash
■ DATA[15..0] bus is a bidirectional bus used to supply and read data to and from
the flash, with the flash output controlled by nOE
The serial clock (DCLK) generated by Cyclone III devices controls the entire
configuration cycle and provides timing for the parallel interface. Cyclone III devices
use a 40-Mhz internal oscillator to generate DCLK. The oscillator is the same oscillator
used in the AS configuration scheme. The active DCLK output frequency is listed in
Table 9–8 on page 9–14.
Multi-Device AP Configuration
You can cascade multiple Cyclone III devices using the chip-enable (nCE) and chip-
enable-out (nCEO) pins. The first device in the chain must have its nCE pin connected to
GND. Connect its nCEO pin to the nCE pin of the next device in the chain. Use an
external 10-k pull-up resistor to pull the nCEO signal high to its V_CCIO level to help
the internal weak pull-up resistor. When the first device captures all its configuration
data from the bitstream, it drives the nCEO pin low, enabling the next device in the
chain. You can leave the nCEO pin of the last device unconnected or use it as a user I/O
pin after configuration if the last device in the chain is a Cyclone III device. The
nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA[15..8], and DATA[7..0] pins of each device
in the chain are connected (Figure 9–9 on page 9–28 and Figure 9–10 on page 9–29).
The first Cyclone III device in the chain, as shown in Figure 9–9 on page 9–28 and
Figure 9–10 on page 9–29, is the configuration master device and controls the
configuration of the entire chain. Connect its MSEL pins to select the AP configuration
scheme. The remaining Cyclone III devices are used as configuration slaves. Connect
their MSEL pins to select the FPP configuration scheme. Any other Altera device that
supports FPP configuration can also be part of the chain as a configuration slave.
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1