EP3C120F484C7 Datasheet, PDF (64/274 Pages) Altera Corporation – Cyclone III Device Handbook

5–4
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Clock Networks
If you do not use dedicated clock pins to feed the GCLKs, you can use them as
general-purpose input pins to feed the logic array. However, when using them as
general-purpose input pins, they do not have support for an I/O register and must
use LE-based registers in place of an I/O register.
f For more information about how to connect the clock and PLL pins, refer to the
Cyclone III Device Family Pin Connection Guidelines on the Altera^® website.
Clock Control Block
The clock control block drives GCLKs. Clock control blocks are located on each side of
the device, close to the dedicated clock input pins. GCLKs are optimized for
minimum clock skew and delay.
Table 5–2 lists the sources that can feed the clock control block, which in turn feeds the
GCLKs.
Table 5–2. Clock Control Block Inputs
Input
Dedicated clock inputs
Dual-purpose clock
(DPCLK and CDPCLK)
I/O input
PLL outputs
Internal logic
Description
Dedicated clock input pins can drive clocks or global signals, such as
synchronous and asynchronous clears, presets, or clock enables onto
given GCLKs.
DPCLK and CDPCLK I/O pins are bidirectional dual function pins that
are used for high fan-out control signals, such as protocol signals,
TRDY and IRDY signals for PCI, via the GCLK. Clock control blocks
that have inputs driven by dual-purpose clock I/O pins are not able to
drive PLL inputs.
PLL counter outputs can drive the GCLK.
You can drive the GCLK through logic array routing to enable internal
logic elements (LEs) to drive a high fan-out, low-skew signal path.
Clock control blocks that have inputs driven by internal logic are not
able to drive PLL inputs.
In the Cyclone III device family, dedicated clock input pins, PLL counter outputs,
dual-purpose clock I/O inputs, and internal logic can all feed the clock control block
for each GCLK.
1 Normal I/O pins cannot drive the PLL input clock port.
The output from the clock control block in turn feeds the corresponding GCLK. The
GCLK can drive the PLL input if the clock control block inputs are outputs of another
PLL or dedicated clock input pins. The clock control blocks are at the device
periphery; there are a maximum of 20 clock control blocks available per Cyclone III
device family.
The control block has two functions:
■ Dynamic GCLK clock source selection (not applicable for DPCLK or CDPCLK and
internal logic input)
■ GCLK network power down (dynamic enable and disable)
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation